Semiconductor Package Terminal Protection for Wafer-Level Impact Resistance
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Solution Overview
Problem
Semiconductor chips in wafer level packages are exposed and vulnerable to external impacts during sorting and testing, leading to mechanical damage.
Innovation Solution
A semiconductor package design with a protection member covering side surfaces of connection terminals and a mold member that exposes lower surfaces, using materials with matched thermal expansion coefficients to prevent mechanical damage and enhance reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the semiconductor chip is exposed in wafer level package, then the form factor is small and I/O length is short, but the chip is vulnerable to external impact and mechanical damage
Solution Approach 1:
A protection member is introduced as an intermediary element between the connection terminals and the external environment. This protection member covers the side surfaces of the connection terminals while exposing their lower surfaces, providing mechanical protection without compromising electrical connection or thermal dissipation functionality
Solution Approach 2:
The protection member is designed with selective coverage - it covers the side surfaces of the connection terminals to protect them from mechanical damage, while deliberately exposing the lower surfaces to maintain electrical connection and thermal dissipation. This localized protection approach addresses the vulnerability issue without sacrificing functional performance
2Reliability
If a protection member covers the connection terminals, then mechanical protection is improved, but thermal dissipation may be affected
Solution Approach 1:
The protection member is designed with differential coverage - covering side surfaces for mechanical protection while exposing lower surfaces to maintain thermal dissipation pathways. This localized quality differentiation resolves the contradiction between protection and heat management
Solution Approach 2:
The protection member is designed with specific geometric parameters (covering side surfaces while exposing lower surfaces) and material properties (coefficient of thermal expansion matched to connection terminals) to simultaneously achieve mechanical protection and maintain thermal dissipation efficiency
3Reliability
If mold member covers the semiconductor device, then mechanical protection is improved, but thermal dissipation and electrical connection may be compromised
Solution Approach 1:
The mold member is designed with selective coverage - covering the side surface of the semiconductor device for mechanical protection while exposing the lower surface to maintain thermal dissipation and electrical connection pathways. This localized protection strategy resolves the contradiction between mechanical strength and thermal/electrical performance
4Adaptability or versatility
If protection member and mold member have different thermal expansion coefficients, then material selection flexibility is improved, but thermal stress and cracking risk increase
Solution Approach 1:
The protection member is designed with a specific coefficient of thermal expansion parameter that is substantially equal to or smaller than that of the connection terminals. This parameter optimization minimizes thermal stress during temperature changes, preventing cracking while maintaining material selection flexibility for other properties
Solution Approach 2:
The patent explicitly considers thermal expansion characteristics in material selection - the protection member's coefficient of thermal expansion is matched to the connection terminals to prevent relative expansion/contraction during temperature cycling, thereby avoiding crack formation at the interface
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design improves mechanical protection and thermal dissipation while maintaining reliability by using a protection member with a specific thermal expansion coefficient, reducing the risk of cracks and contamination, and enhancing board-level reliability.
Implementation Method 1
a protection member on the first surface of the semiconductor device and partially covers side surfaces of the plurality of connection terminals
Implementation Method 2
a mold member that covers a side surface of the semiconductor device and a portion of the protection member
Implementation Method 3
a difference between a coefficient of thermal expansion of the protection member and a coefficient of thermal expansion of the plurality connection terminals is smaller than a difference between a coefficient of thermal expansion of the mold member and the coefficient of thermal expansion of the plurality of connection terminals
Implementation Method 4
the protective member exposes lower surfaces of the plurality of connection terminals... the mold member exposes a second surface of the semiconductor device
Data Source
AI summary
Provided is a semiconductor package with improved reliability. The semiconductor package includes: a plurality of connection terminals on a first surface of the semiconductor device; a protection member on the first surface of the semiconductor device and partially covers side surfaces of the plurality of connection terminals such that the protective member exposes lower surfaces of the plurality of connection terminals; and a mold member that covers a side surface of the semiconductor device and a portion of the protection member such that the mold member does not cover the lower surfaces of the plurality of connection terminals.