Semiconductor Module Terminal Layout for Balanced Parasitic Inductance
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Solution Overview
Problem
There is a demand for energy-saving, sophisticated, and smaller electronic devices, which requires improved performance and reduced size of semiconductor modules.
Innovation Solution
A semiconductor module with a specific module structure that includes a conductive substrate with semiconductor elements bonded to it, conducting members forming the path of main circuit current, and input and output terminals offset in specific directions to equalize parasitic inductance components and current distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If semiconductor modules are reduced in size to meet demand for smaller electronic devices, then device compactness is improved, but parasitic inductance components increase and current distribution becomes uneven
Solution Approach 1:
The patent applies asymmetry by offsetting the input terminals and output terminals from the conductive substrate in different directions. Specifically, the first input terminal and second input terminal are offset in one sense of a first direction, while the output terminal is offset in another sense of the first direction. This asymmetric terminal arrangement equalizes parasitic inductance components along the main circuit current path without requiring increased module size.
Solution Approach 2:
The patent utilizes spatial dimensionality by arranging semiconductor elements in multiple directions relative to the conductive substrate. The first plurality of semiconductor elements are spaced apart along a second direction perpendicular to both the thickness direction and the first direction, while the second plurality are spaced apart along the thickness direction. This multi-dimensional arrangement optimizes current distribution and reduces parasitic inductance within a compact footprint.
2Area of stationary object
If semiconductor elements are densely packed to reduce module size, then area utilization is improved, but current distribution uniformity deteriorates
Solution Approach 1:
The patent applies local quality by creating distinct spatial zones for different semiconductor element groups. The first plurality of semiconductor elements are positioned and spaced differently from the second plurality, with each group having optimized spacing in specific directions. This localized arrangement ensures that current distribution remains uniform across the substrate even as overall density increases to reduce module size.
Data Source
AI summary
A semiconductor module includes: a first conductive portion; a second conductive portion spaced from the first conductive portion in a first direction; first semiconductor elements electrically bonded to the first conductive portion and mutually spaced in a second direction perpendicular to the first direction; and second semiconductor elements electrically bonded to the second conductive portion and mutually spaced in the second direction. The semiconductor module further includes: a first input terminal electrically connected to the first conductive portion; a second input terminal of opposite polarity to the first input terminal; and an output terminal opposite from the two input terminals in the first direction and electrically connected to the second conductive portion. The semiconductor module further includes: a first conducting member connected to the first semiconductor elements and second conductive portion; and a second conducting member connected to the second semiconductor elements and second input terminal.