Semiconductor Package Terminal Layout for Faster Switching
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Solution Overview
Problem
Existing semiconductor devices face challenges in optimizing switching characteristics and achieving higher power density due to inadequate consideration of signal terminal heights and increased wire lengths, which generate heat and affect current balance.
Innovation Solution
The semiconductor device features a configuration where the gate terminal and source sense terminal are at different heights, with the source terminal being the lowest, and wires are arranged to minimize heat generation and improve current balance, allowing for complex circuit configurations and optimized switching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If signal terminals (gate terminal and source sense terminal) are arranged at the same height level as main terminals, then wire lengths can be reduced, but switching characteristics cannot be optimized
Solution Approach 1:
The patent applies dimensional change by arranging signal terminals (gate terminal and source sense terminal) at a different height level than main terminals (source terminal and drain terminal). Specifically, signal terminals are positioned on an upper level while main terminals are on a lower level, creating a multi-level terminal structure. This vertical dimensionality allows independent optimization of signal terminals for switching characteristics without being constrained by the positioning requirements of main terminals, thereby resolving the contradiction between optimizing switching characteristics and maintaining simple terminal arrangement.
2Reliability
If main terminals are arranged on an upper step and signal terminals on a lower step, then switching characteristics can be optimized, but wire lengths increase and heat generation increases
Solution Approach 1:
The patent applies asymmetry by creating an asymmetric multi-level terminal arrangement where signal terminals and main terminals are positioned at different height levels. The asymmetric structure places signal terminals (gate terminal and source sense terminal) on an upper level closer to the semiconductor chip, while main terminals are on a lower level. This asymmetric positioning optimizes wire lengths for signal terminals to improve switching characteristics, while the lower position of main terminals provides thermal management benefits, thereby resolving the contradiction between optimizing switching characteristics and reducing heat generation.
3Power
If wire lengths are reduced to increase power density, then heat generation decreases, but switching characteristics may be compromised
Solution Approach 1:
The patent applies segmentation by dividing terminals into two distinct groups positioned at different height levels: signal terminals (gate terminal and source sense terminal) on an upper level, and main terminals (source terminal and drain terminal) on a lower level. This segmentation allows independent optimization of wire lengths for each terminal type. Signal terminals can have shorter wires to optimize switching characteristics, while main terminals are positioned to manage heat generation, thereby achieving both high power density and optimized switching characteristics simultaneously.
Data Source
AI summary
A semiconductor device includes: a plurality of semiconductor chips mounted to an insulating substrate; and a case housing them. The case has a gate terminal, a source sense terminal, a source terminal, and a drain terminal. The gate terminal and the source sense terminal are at different heights, and the source terminal is at a smaller height than the gate terminal and the source sense terminal.