Semiconductor Terminal Layout for Low-Inductance Power Modules
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Solution Overview
Problem
Existing semiconductor devices face challenges in reducing one-turn loop inductance (one-turn Ls) while minimizing terminal position displacement and connection failures, particularly in structures with large-power switching elements.
Innovation Solution
A semiconductor device configuration with conductive plates and conductors arranged in specific directions, incorporating dummy terminals and connection portions to stabilize conductor positions, and exposing P and N terminals to reduce one-turn Ls and prevent terminal drooping during manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If terminals are fixed only at entrance parts on lead frame, then mounting process is simplified, but terminal ends drop by self-weight causing insufficient solder joining and connection failure
Solution Approach 1:
The patent applies preliminary action by fixing terminals at multiple positions (both entrance and exit parts) on the lead frame before the soldering process. This pre-fixing prevents terminal drooping during manufacturing, ensuring proper solder joining without compromising the simplified mounting process approach.
2Device complexity
If terminals are fixed only at entrance parts, then device structure is simplified, but terminal position displacement and connection failure occur due to insufficient solder
Solution Approach 1:
The patent implements preliminary action by pre-fixing terminals at multiple positions on the lead frame before soldering. This ensures terminal positions remain accurate throughout the manufacturing process, preventing displacement and connection failures while maintaining reasonable structural simplicity.
3Object-affected harmful factors
If P terminals and N terminals are led out in parallel from both left and right sides, then one-turn Ls is reduced, but length between lateral wiring terminals becomes four times longer
Solution Approach 1:
The patent applies dimensionality change by transitioning from a lateral lead-out configuration to a longitudinal lead-out configuration where P and N terminals are positioned at opposite ends along the length of the device. This reduces the wiring loop area and inductance while avoiding the excessive wiring length problem of lateral configurations.
4Length of moving object
If control terminals are arranged in the long-side direction, then device length is constrained, but device downsizing is hampered
Solution Approach 1:
The patent applies dimensionality change by reorienting the control terminal arrangement from the long-side direction to the short-side direction. This allows the device to be downsized in the long-side dimension while still accommodating all necessary control terminals, thereby improving overall device compactness.
Data Source
AI summary
This semiconductor device includes a first dummy terminal extending from a second conductor toward one side in a first direction, a second dummy terminal extending from a fourth conductor toward another side in the first direction, and a third dummy terminal extending from a third conductor through between a third conductive plate and a fourth conductive plate toward one side in a second direction, and connected to a second AC terminal. In a state in which ends of the first dummy terminal, the second dummy terminal, first control terminals, second control terminals, second AC terminals, first AC terminals, N terminals, and P terminals are exposed, the first conductive plate, a second conductive plate, the third conductive plate, the fourth conductive plate, first switching elements, second switching elements, a first conductor, the second conductor, the third conductor, and the fourth conductor are sealed by a resin member.