Semiconductor Device External Terminal Parallel Arrangement
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Solution Overview
Problem
In semiconductor devices, the mutual inductance between busbars and conductors in semiconductor modules is not effectively reduced, leading to increased impedance and material costs due to long pin-shaped terminals and mismatched thermal expansion coefficients between resin and circuit substrates.
Innovation Solution
A semiconductor device configuration with a flat plate portion of the external terminal parallel to the second circuit pattern layer, reducing mutual inductance, and using a sealing member with a reduced thickness to minimize resin usage and thermal stress, while shortening pin-shaped terminals and arranging them in parallel with the circuit pattern layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a busbar is arranged in a direction crossing among multiple semiconductor modules and conductors flow in a longitudinal direction, then the modules can be connected in parallel to increase capacity, but the mutual inductance between busbar and conductors increases due to intersecting current directions
Solution Approach 1:
The patent changes the spatial arrangement of conductors from a longitudinal direction (parallel to module length) to a transverse direction (parallel to module width), aligning them with the busbar orientation. This dimensional repositioning ensures current flows in the same direction throughout the parallel connection path, eliminating mutual inductance while maintaining increased power capacity through parallel module configuration
2Reliability
If pin-shaped terminals are made longer to connect semiconductor elements to external terminals, then electrical connection is achieved, but the inductance increases due to extended wiring length
Solution Approach 1:
The patent repositions the semiconductor element from a vertical mounting orientation to a horizontal mounting orientation on the circuit substrate. This dimensional change allows the pin-shaped terminal to extend horizontally in the same direction as the external terminal, dramatically shortening the effective wiring length and reducing inductance while maintaining reliable electrical connection
3Reliability
If a thick sealing member is used to seal the semiconductor device, then reliability and protection are improved, but the amount of resin increases and thermal stress from expansion coefficient mismatch increases
Solution Approach 1:
The patent optimizes the thickness parameter of the sealing member to a minimal value that still provides adequate sealing and protection. By reducing the resin thickness, the total amount of resin is minimized and the thermal mass is reduced, thereby decreasing thermal stress from expansion coefficient mismatch between the resin sealing member and the circuit substrate while maintaining sufficient reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration decreases mutual inductance, impedance, and material costs, while enhancing high-speed operation and reliability by aligning current directions and reducing thermal stress.
Implementation Method 1
a current direction of the busbar intersects with a current direction of the conductors in the modules, and a mutual inductance of these is not decreased
Implementation Method 2
a sealing member that seals the first circuit substrate, the semiconductor element, the second circuit substrate, and the connecting pin using resin
Implementation Method 3
mismatched thermal expansion coefficients between resin and circuit substrates
Data Source
AI summary
A semiconductor device includes circuit substrates 3 and 9 including circuit pattern layers 3c/9b, a semiconductor element 5 mounted to the circuit pattern layer 3c, a connecting pin 7 connecting the semiconductor element 5 to the circuit pattern layer 9b, a pin-shaped terminal 17 connected to the circuit pattern layer 9b, a sealing member 2 sealing the circuit substrates 3 and 9, the semiconductor element 5, and the connecting pin 7, and an external terminal 27 including a flat plate portion 27s and an extending portion 27t bent from the flat plate portion 27s and extends away from the circuit substrate 9, in which the flat plate portion 27s is connected to the pin-shaped terminal 17 and arranged in parallel with the circuit pattern layer 9b, and the extending portion 27t is provided in a range of a width in a transverse direction of the sealing member 2.