Semiconductor Terminal Arrangement for Wire Bonding Stability

The patent transitions from a conventional single-row terminal arrangement to a multi-dimensional arrangement where terminals are organized in multiple rows and columns on the wiring substrate. This spatial reorganization allows more terminals to be packed into a smaller planar area by utilizing both horizontal and vertical dimensions, thereby increasing functionality without proportionally increasing the substrate size.

The patent employs a nested arrangement where the semiconductor chip is mounted on the wiring substrate, and terminals are arranged in concentric patterns around the chip mounting area. This nesting approach maximizes the utilization of available substrate area by placing terminals in multiple rings or rows at different distances from the center, enabling higher terminal density within a compact footprint.

The patent applies different terminal width specifications to different terminal groups based on their functional requirements and wire coupling conditions. Specifically, terminals arranged in certain rows (e.g., first and second rows) are given a first width, while terminals in other rows (e.g., third row) are given a second width that is larger than the first width. This local differentiation ensures that terminals requiring more stable wire coupling have larger margins, while maintaining overall compact substrate size.

The patent introduces asymmetric terminal sizing where not all terminals have the same dimensions. By making certain terminals wider than others, the design creates an asymmetric pattern that optimizes wire coupling reliability for critical connections while maintaining space efficiency for less critical connections. This asymmetric approach breaks the uniformity constraint and allows targeted reinforcement of coupling margins where needed.