Semiconductor External Terminals With Varying Heights for CTE Stress Relief
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The semiconductor industry faces manufacturing challenges due to stress derived from differences in coefficients of thermal expansion (CTEs) between various layers in new packaging technologies, leading to risks of delamination and cold joints.
Innovation Solution
The implementation of a manufacturing method that involves forming external terminals with varying heights over a circuit substrate using a patterned mask layer with varying openings, which helps in adjusting the contact area and stress levels of the external terminals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If new packaging technologies with multiple layers are used to achieve higher integration density, then more components can be integrated into a given area, but stress derived from differences in coefficients of thermal expansion causes delamination and cold joints
Solution Approach 1:
The patent applies local quality by creating a gradient in the thickness of the underfill material or encapsulant layer beneath the external terminals. Instead of using a uniform thickness throughout, the layer thickness is varied locally - thinner in regions where external terminals are located and thicker in other areas. This local variation in thickness compensates for the stress caused by CTE differences, allowing the package to maintain both high integration density and joint reliability.
2Ease of manufacture
If external terminals are formed with uniform height and contact area, then manufacturing is simplified, but stress distribution becomes uneven leading to delamination and cold joints
Solution Approach 1:
The patent applies parameter changes by modifying the geometric parameters of the underfill or encapsulant layer - specifically the thickness parameter - to optimize stress distribution. By changing the thickness parameter of the underfill layer in different regions of the package, the patent achieves more uniform stress distribution across external terminals without complicating the terminal fabrication process itself. The uniform terminal geometry is maintained while the underlying support structure is varied.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the risk of delamination and cold joints by optimizing the stress distribution and ensuring improved reliability and electrical performance of the semiconductor packages.
Implementation Method 1
the different layers making up the interconnection in the packages have different coefficients of thermal expansion (CTEs). As a result, a relatively large stress derived from this difference is exhibited on the joint area
Data Source
AI summary
A semiconductor structure and a manufacturing method thereof are provided. The method includes the following steps. A plurality of conductive balls is placed over a circuit substrate, where each of the conductive balls is placed over a contact area of one of a plurality of contact pads that is accessibly revealed by a patterned mask layer. The conductive balls are reflowed to form a plurality of external terminals with varying heights connected to the contact pads of the circuit substrate, where a first external terminal of the external terminals formed in a first region of the circuit substrate and a second external terminal of the external terminals formed in a second region of the circuit substrate are non-coplanar.