Semiconductor Package Terminals With Micro Dimples to Reduce Cracking
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Solution Overview
Problem
Conventional semiconductor packages face issues of excess cost, decreased reliability, and large package sizes due to stress-related problems such as cracking, which are not adequately addressed by existing technologies.
Innovation Solution
The introduction of a substrate outward terminal design featuring a multi-via or multi-stage terminal structure with conductive pad vias and dielectric vias, which reduces stress by minimizing the depth of micro dimples, thereby preventing larger dimples and maintaining a uniform thickness of the conductive structure, and includes a method for manufacturing these terminals using processes like electroplating and photoresist patterning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional substrate terminal designs are used, then manufacturing is simpler, but stress-related cracking occurs and reliability decreases
Solution Approach 1:
The substrate terminal is divided into multiple segments: pad conductive vias, pad dielectric vias, and conductor regions with micro dimples. This segmentation distributes stress across multiple smaller components rather than concentrating it in a single large terminal structure, preventing cracking while maintaining electrical functionality.
Solution Approach 2:
The terminal structure incorporates local variations in geometry and material properties, specifically micro dimples with controlled depth (less than 20% of terminal width) in the conductor regions. These localized features modify stress distribution at critical points without affecting the overall terminal structure, enhancing reliability through targeted stress management.
2Reliability
If larger dimples are formed in substrate terminals, then stress is concentrated, but this leads to cracking and reduced reliability
Solution Approach 1:
The patent严格控制微凹坑深度参数，使其小于终端宽度的20%。这一参数变化使得微凹坑能够缓解应力集中，同时不会过度削弱导体的机械强度。通过精确控制这一关键几何参数，实现了应力分散和结构强度的最优平衡。
3Reliability
If multi-via or multi-stage terminal structures are implemented, then stress is reduced and reliability improves, but manufacturing complexity increases
Solution Approach 1:
The patent employs preliminary patterning actions through photoresist coating and etching to define the complex multi-via terminal structure before conductor deposition. The micro dimples are formed through controlled etching processes that prepare the substrate in advance, allowing subsequent electroplating to follow predetermined patterns. This preliminary structuring simplifies the overall manufacturing sequence despite the terminal's geometric complexity.
Solution Approach 2:
The patent replaces complex mechanical alignment processes with electroplating-based conductor formation. The electroplating process naturally follows the patterned seed layers and photoresist masks, automatically achieving precise conductor placement and micro dimple formation without requiring complex mechanical positioning equipment or multi-step alignment procedures.
4Reliability
If uniform conductor thickness is maintained, then manufacturing is simpler, but stress-related cracking occurs
Solution Approach 1:
The conductor structure incorporates local thickness variations through micro dimples with controlled depth. These localized thinning regions are strategically positioned to relieve stress concentration points, while the majority of the conductor maintains uniform thickness for optimal electrical performance and manufacturability. This local quality variation resolves the contradiction between uniformity and stress resistance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces the likelihood of cracking in semiconductor devices by minimizing dimple depth and maintaining a uniform conductor thickness, enhancing reliability and reducing package size while maintaining electrical coupling and protection from environmental exposure.
Implementation Method 1
The substrate outward terminal comprises one of a multi-via terminal or a multi-stage terminal. Both substrate outward terminal structures reduce the size of dimples formed in the substrate outward terminal thereby reducing stress.
Implementation Method 2
includes a method for manufacturing these terminals using processes like electroplating and photoresist patterning
Data Source
AI summary
In one example, an electronic device includes a substrate having a conductive structure. The conductive structure includes a substrate inward terminal at a first side of the substrate and a substrate outward terminal at a second side of the substrate. The substrate includes a dielectric structure with a first opening is at the second side. An electronic component is at the first side of the substrate and is electrically coupled to the substrate inward terminal, and an encapsulant encapsulates the electronic component. The substrate outward terminal comprises one of a multi-via terminal or a multi-stage via. The multi-via terminal includes pad conductive vias in the first opening a pad dielectric via interposed between the pad conductive vias in the first opening and a conductor comprising a conductor top side with micro dimples over the pad conductive vias and the pad dielectric via. The multi-stage terminal includes a pad base within the first opening having a pad base top side recessed below an upper surface the first dielectric and a pad head coupled to the pad base within the first opening, the pad head having a pad head top side with a micro dimple. Other examples and related methods are also disclosed herein.