Semiconductor Termination Region Withstand Voltage Optimization
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Solution Overview
Problem
Increasing the withstand voltage in semiconductor devices requires more P-type ring layers, leading to increased chip area, high electric field generation, and complex manufacturing processes, with a narrow allowable range for P-type layer dose causing defects and high production costs.
Innovation Solution
A semiconductor device with a termination region featuring regularly arranged ring-shaped P-type ring layers, divided into units with constant width, where the total number of P-type impurities and unit width satisfy specific relationships to maintain target withstand voltage, reducing chip area and simplifying manufacturing while improving turn-off breaking capability and dose range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If the number of P-type ring layers is increased to increase withstand voltage, then the withstand voltage is improved, but the chip area increases
Solution Approach 1:
The patent changes the parameters of the P-type ring layers, specifically making the width of successive P-type ring layers decrease linearly from the innermost layer outward. This parameter change allows achieving the required withstand voltage with fewer layers, thereby reducing chip area while maintaining electrical performance
Solution Approach 2:
The patent applies different width characteristics to different regions of the P-type ring layers. The innermost layers have larger widths to handle higher electric fields near the active region, while outer layers have progressively smaller widths, optimizing the distribution of electrical stress and reducing overall chip area
2Strength
If the number of P-type ring layers is increased to increase withstand voltage, then the withstand voltage is improved, but the manufacturing process becomes more complicated
Solution Approach 1:
The patent merges multiple P-type ring layers into a single ion implantation process by defining their widths and positions in advance. This allows forming all required P-type ring layers simultaneously during manufacturing, significantly simplifying the process compared to forming each layer separately
3Strength
If the dose of P-type layer is outside the allowable range, then a high electric field is generated limiting the upper limit of withstand voltage, but process control becomes difficult with high defect ratio
Solution Approach 1:
The patent changes the structural parameters of P-type ring layers (widths decreasing linearly from innermost outward) to widen the allowable dose range. This parameter optimization ensures that even with normal process variations in ion implantation dose, the electric field distribution remains within acceptable limits, improving manufacturing precision and reducing defects
Data Source
AI summary
The termination region includes a ring region (LNFLR). A plurality of ring-shaped P-type ring layers are regularly arranged in the ring region (LNFLR). The ring region (LNFLR) is divided into a plurality of units which include the plurality of P-type ring layers respectively. A width of each unit is constant. A total number of P-type impurities in the ring region (LNFLR) is N, the target withstand voltage is BV [V], a width of each unit is SandL [μm], and the number of the plurality of units is num, following relationships are satisfied. N≧(M×BV)γ, M=104 to 105, γ=0.55 to 1.95, SandL×num×Ecri≧2×α×BV, Ecri=2.0 to 3.0×105 [V/cm], α=100 to 101. Widths of the P-type ring layers of the plurality of units linearly decrease toward an outside of the termination region.