Semiconductor Test Apparatus PLE Board Signal Integrity
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Solution Overview
Problem
Existing semiconductor device test apparatuses face issues with signal loss and reduced accuracy due to noise and jitter in test signals, which affect the reliability of System on Chip (SoC) testing.
Innovation Solution
A semiconductor device test apparatus is designed with physical layer equalizing (PLE) boards and a dual signal testing system that includes AC and DC controllers, featuring filter circuits to reduce jitter and noise, and a DC signal relay circuit with a bead to prevent AC signals from interfering with DC tests, enhancing signal integrity and accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If physical layer equalizing (PLE) boards are added to reduce signal loss, then signal integrity improves, but device complexity increases
Solution Approach 1:
The PLE board is integrated within the probe interface board structure, with the equalizer circuit nested inside the existing board architecture. This allows signal equalization functionality to be added without requiring a completely separate external device, thereby improving signal integrity while minimizing the increase in overall device complexity.
Solution Approach 2:
The PLE board serves multiple functions: it equalizes signals, reduces loss, and can be configured for different testing scenarios. By making the equalizer circuit multi-functional and adaptable to various test requirements, the patent achieves improved signal integrity without proportionally increasing complexity, as the same hardware structure serves multiple purposes.
2Measurement precision
If multiple PLE boards are mounted to improve signal loss rate, then testing accuracy improves, but available space is consumed
Solution Approach 1:
Instead of placing multiple PLE boards side-by-side in the same plane, the patent utilizes vertical stacking and three-dimensional space utilization. The PLE boards are mounted in a configuration that exploits the Z-dimension (vertical direction) rather than only the X-Y plane, allowing multiple equalizer boards to be accommodated without proportionally increasing the footprint area, thus maintaining testing accuracy while preserving available space.
3Adaptability or versatility
If AC and DC testing are performed using separate circuits, then testing versatility improves, but signal interference may occur
Solution Approach 1:
The patent introduces a bead as an intermediary component in the DC signal relay circuit. This bead acts as a filter or barrier that prevents AC signals from coupling into the DC testing path. By placing this intermediary element, the system maintains both AC and DC testing capabilities (versatility) while eliminating the harmful interference between the two signal types.
Data Source
AI summary
A semiconductor device test apparatus for improving a loss rate of a test signal in testing a device under test is provided. The semiconductor device test apparatus includes a probe interface board, a pogo block disposed on the probe interface board and electrically connected to a device under test, an equipment board disposed under the probe interface board, an alternating current (AC) controller, transferring and receiving an AC signal for performing an AC test on at least one of the device under test and the pogo block, being mounted on the equipment board, and a physical layer equalizing (PLE) board disposed between the probe interface board and the equipment board, a first equalizing circuit, decreasing loss of the AC signal, being mounted on the PLE board.