Semiconductor Test Circuit Array With Two-Dimensional Transistor Grid
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Solution Overview
Problem
Existing semiconductor devices face challenges in effectively testing electrical characteristics and semiconductor processes due to the need for precise measurement of integrated circuits, which is crucial for ensuring proper functionality and manufacturing quality.
Innovation Solution
A semiconductor device design incorporating a test circuit array with transistors arranged in multiple directions, source and drain lines, word lines, and well driving lines, along with pad regions for efficient electrical connection and signal application, allowing for the precise measurement of electrical characteristics and process evaluation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If transistors are arranged in a two-dimensional array with source and drain lines extending in one direction, then the device structure is simplified, but the measurement precision of electrical characteristics is insufficient for highly integrated semiconductor devices
Solution Approach 1:
The patent transitions from a one-dimensional arrangement of source and drain lines to a two-dimensional grid structure by introducing word lines extending in a direction perpendicular to the source and drain lines. This dimensional change enables selective access to individual transistors in the array through the intersection of word lines and source/drain lines, thereby improving measurement precision without excessive complexity increase.
Solution Approach 2:
The test circuit is segmented into multiple independently controllable word lines and source/drain lines, allowing selective activation of specific transistor rows and columns. This segmentation enables precise measurement of individual transistors or groups of transistors within the two-dimensional array, enhancing measurement precision while maintaining manageable circuit complexity.
2Productivity
If multiple test circuits are integrated on a single wafer, then productivity increases, but the area occupied by each test circuit decreases, limiting measurement capabilities
Solution Approach 1:
The two-dimensional transistor array with word lines and source/drain lines creates a universal test structure that can evaluate multiple transistors simultaneously through selective line activation. This multi-functional design allows a single compact test circuit to replace multiple dedicated test circuits, increasing productivity while reducing the area required per test function.
Solution Approach 2:
Multiple test functions are merged into a single integrated test circuit array where shared word lines and source/drain lines serve multiple transistors. This combining approach eliminates redundant circuitry, reduces the total area required for testing, and enables higher productivity by allowing concurrent measurement of multiple devices.
3Area of stationary object
If pad regions are positioned close to the test circuit array, then the area efficiency improves, but the distance for voltage application and signal measurement increases resistance and reduces measurement accuracy
Solution Approach 1:
The source and drain lines act as intermediaries that provide low-resistance pathways between the pad regions and the transistor measurement points. These dedicated interconnection lines minimize the impact of distance by providing controlled, low-impedance routes for voltage application and signal measurement, thereby maintaining measurement accuracy despite the compact layout.
Solution Approach 2:
The patent employs different line width characteristics for different portions of the interconnection structure. The source and drain lines are designed with adequate width in the region spanning from pad to transistor to maintain low resistance, while other areas of the circuit use optimized dimensions for their specific functions. This local optimization of geometric parameters balances area efficiency with electrical performance.
Data Source
AI summary
A semiconductor device may include a semiconductor substrate; a test circuit array region; a pad region on the semiconductor substrate and at at least a first side of the test circuit array region and outside of the test circuit array region, transistors arranged in the test circuit array region in a first direction and a second direction perpendicular to the first direction, source lines spaced apart from each other in the second direction, each of the source lines extending in the first direction and electrically connected to corresponding source electrodes of the transistors, and drain lines spaced apart from each other in the second direction, each of the drain lines extending in the first direction and electrically connected to drain electrodes of the transistors.