Semiconductor Test System Using Common Bus for BIST Control
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Solution Overview
Problem
The complexity of controlling multiple Built-In Self-Test (BIST) circuits in semiconductor devices complicates external testing, as each BIST circuit requires a test pin and synchronization with external test apparatuses, making it difficult to manage and test various types of circuits within a single semiconductor device.
Innovation Solution
A test system with internal test circuits connected via a common bus, allowing a device control section to receive external signals and control the BIST circuits, and a test apparatus that synchronizes the internal test circuits with external test circuits using a common bus and synchronization control section.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple BIST circuits are provided in a semiconductor device to test various circuits, then the testing capability is improved, but the device complexity increases and control becomes difficult
Solution Approach 1:
The patent merges multiple BIST circuits into a unified system controlled by a single external test apparatus. The BIST circuits are integrated with test circuits that can be controlled through common control signals, reducing the need for separate control mechanisms for each BIST circuit and simplifying the overall control architecture.
Solution Approach 2:
The patent implements a universal control interface where a single external test apparatus can control multiple different types of BIST circuits (logic circuit BIST, memory circuit BIST, analog circuit BIST) through standardized control signals. This multi-functional approach allows one test apparatus to handle various testing needs without requiring separate dedicated control paths for each BIST circuit type.
2Ease of operation
If a test pin is provided for each BIST circuit to enable external control, then the controllability is improved, but the number of required pins increases and the device structure becomes more complex
Solution Approach 1:
The patent combines multiple test pin functions into a single integrated interface. Instead of providing separate test pins for each BIST circuit, the invention uses one external test apparatus that can sequentially or simultaneously control multiple BIST circuits through shared control signals, dramatically reducing the total number of required test pins.
Solution Approach 2:
The external test apparatus is designed with universal control capabilities that allow it to interface with and control multiple different BIST circuit types through a standardized single interface. This multi-functional test apparatus can adapt its control signals to work with logic BIST, memory BIST, analog BIST, and other circuit types without requiring dedicated pins for each.
3Measurement precision
If BIST circuits are synchronized with external test circuits, then the testing accuracy is improved, but the synchronization complexity increases
Solution Approach 1:
The patent introduces an intermediary control mechanism where the external test apparatus acts as a mediator between the external test signals and the internal BIST circuits. This intermediary interface manages the synchronization by translating external test signals into coordinated control signals that simultaneously or sequentially activate multiple BIST circuits, thereby simplifying the synchronization process while maintaining testing accuracy.
4Quantity of substance
If the area occupied by each BIST circuit is decreased to fit more circuits, then the quantity of BIST circuits is improved, but the control difficulty increases
Solution Approach 1:
The patent merges the control functions for multiple compact BIST circuits into a single integrated control path. By using one external test apparatus that can address and control multiple BIST circuits through standardized interfaces, the invention enables dense packing of BIST circuits without proportionally increasing control complexity, as all circuits can be managed through unified control signals.
Data Source
AI summary
Provided is a test system that tests a device under test, including a plurality of internal test circuits that are provided inside the device under test and that are used for testing an operation circuit of the device under test; a device control section that is electrically connected to the plurality of internal test circuits via a common bus and that controls the plurality of internal test circuits by supplying the common bus with an intra-device control signal corresponding to a received external signal; and a test apparatus that supplies the device control section with the external signal.