Semiconductor Test Circuit Parallel Memory Block Comparison
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Solution Overview
Problem
Semiconductor apparatus test processes often require lengthy periods, and existing parallel test modes do not efficiently shorten this time, impacting product yield.
Innovation Solution
A test circuit with multiple memory blocks and comparison blocks that compare data between memory blocks not sharing word lines, utilizing shared sense amplifiers and logic operations to generate pass/fail signals, improving test reliability and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a parallel test mode is used to process multiple bits data at a time, then test productivity is improved, but test circuit complexity increases due to additional comparison blocks and memory block coordination requirements
Solution Approach 1:
The test circuit is segmented into multiple independent comparison blocks (first comparison block, second comparison block, etc.), each responsible for comparing specific pairs of memory blocks. This segmentation allows parallel processing of different data pairs simultaneously, improving test productivity while distributing circuit complexity across modular units rather than requiring a monolithic complex circuit.
Solution Approach 2:
The patent introduces a dimensional organization of memory blocks arranged in series with alternating pairs assigned to different comparison blocks. By organizing memory blocks in a sequential series and assigning alternating pairs to different comparison units, the system achieves parallel processing capability without proportionally increasing overall circuit complexity, as the structure leverages the existing memory block arrangement.
2Reliability
If multiple comparison blocks are used to compare data between memory blocks, then test reliability is improved through comprehensive data verification, but device complexity increases
Solution Approach 1:
The verification function is segmented across multiple comparison blocks, each handling specific memory block pairs. This segmentation improves reliability by distributing verification tasks, ensuring that errors in one comparison block do not affect others, while maintaining manageable complexity through modular design where each block performs a standardized comparison function.
Solution Approach 2:
Each comparison block is designed with universal functionality to compare data between any assigned pair of memory blocks. The comparison blocks use identical circuit structures and logic operations, allowing them to be replicated and configured for different memory block pairs. This universality improves reliability through consistent verification while avoiding complexity increases from diverse circuit designs.
Data Source
AI summary
A test circuit of a semiconductor apparatus includes a plurality of memory blocks, and a comparison block configured to compare data of two memory blocks, wherein the two of the plurality of memory blocks do not share word lines.