Semiconductor Test Circuit Below Normal Pad
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Solution Overview
Problem
The increasing size of the test circuit region in semiconductor devices for wafer testing poses challenges in guaranteeing a maximum number of net dies and power distribution network (PDN) characteristics, and the physical contact during probe testing causes stress, while existing layouts do not allow for circuits below the pads, leading to inefficiencies.
Innovation Solution
A semiconductor device layout where the test circuit is positioned below the normal pad, with a switching circuit and controller to isolate the test circuit during normal operations, using a test pad for probe contact during wafer testing and a normal pad for power/signal reception, minimizing the test circuit's footprint and ensuring PDN characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the test circuit is formed in the main circuit region to enable wafer testing, then testing capability is improved, but the region occupied by the test circuit increases, reducing the number of net dies
Solution Approach 1:
The test circuit is positioned below the normal pad in the vertical dimension, allowing the test circuit region to overlap with the pad region rather than occupying separate horizontal space. This three-dimensional layout arrangement enables the test circuit to share the pad area, thereby reducing the overall region occupied and increasing the number of net dies that can be formed on the wafer.
2Reliability
If the pad region is used for probe contact during wafer testing, then testing function is improved, but no circuit can be formed below the pad due to physical contact stress, leading to space inefficiency
Solution Approach 1:
The test circuit is placed in the vertical dimension below the normal pad, utilizing the space that would otherwise be unusable due to probe contact stress. This dimensional transition allows the test circuit to occupy the region below the pad without interfering with the probe contact function, effectively converting wasted space into functional circuit area.
Solution Approach 2:
The normal pad serves dual functions: it receives power or signals during normal operation and simultaneously provides structural support and electrical connection for the test circuit positioned below it during wafer testing. This multi-functionality allows the pad region to serve both testing and circuit hosting purposes, eliminating the restriction that no circuit can be formed below the pad.
Data Source
AI summary
A semiconductor device including a test circuit is disclosed. The semiconductor device includes a test pad coupled to a probe of a test device during a wafer test; a normal pad configured to receive a power or a signal during a normal mode; and a test circuit configured to perform a predetermined test operation based on a test signal received through the test pad. The test circuit is disposed below the normal pad.