Semiconductor Test Circuit Parallel Data Storage
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Solution Overview
Problem
The increased soft errors in semiconductor apparatuses due to reduced size lead to longer test times during memory apparatus testing, as multiple memory banks must sequentially pass data through a shared error correction circuit, significantly increasing test duration.
Innovation Solution
A semiconductor apparatus with a control circuit that simultaneously stores data from multiple memory banks during a first sub-test section and sequentially transmits it to an error correction circuit through sub-read paths during a second sub-test section, allowing for parallel processing and reduced test time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple memory banks share one ECC circuit and are tested sequentially, then power consumption and area are optimized, but test time is significantly increased
Solution Approach 1:
The read path is divided into multiple sub-read paths (first sub-read path, second sub-read path, etc.), each capable of independently transmitting data from different memory banks to the ECC circuit. This segmentation allows parallel data transmission while maintaining a shared ECC circuit, thereby reducing test time without significantly increasing overall circuit complexity.
Solution Approach 2:
The patent introduces a temporal dimension to the data transmission process by sequentially activating different sub-read paths during different time periods (first sub-test section, second sub-test section). This time-multiplexed approach allows multiple memory banks to be tested in parallel effectively, as data from different banks are transmitted through different sub-read paths at different times, achieving the goal of reduced test time while keeping the ECC circuit shared.
2Productivity
If all memory banks are tested sequentially through a shared ECC circuit, then device complexity is minimized, but productivity is reduced due to significantly increased test time
Solution Approach 1:
The read path is segmented into multiple independent sub-read paths that can operate in parallel. Each sub-read path is dedicated to transmitting data from specific memory banks, allowing simultaneous testing of multiple banks. This segmentation directly increases test throughput by enabling parallel processing while maintaining a shared ECC circuit for error correction.
Solution Approach 2:
Data from multiple memory banks is simultaneously captured and stored in storage circuits during the first sub-test section before being transmitted through sub-read paths during the second sub-test section. This preliminary data capture prepares the data for parallel transmission and error correction, maximizing test throughput by overlapping data preparation and transmission phases.
Data Source
AI summary
The present technology may include a first storage circuit connected to a plurality of memory banks, an error correction circuit, a read path including a plurality of sub-read paths connected between the plurality of memory banks and the error correction circuit, and a control circuit configured to control data output from the plurality of memory banks to be simultaneously stored in the first storage circuit by deactivating the read path during a first sub-test section, and to control the data stored in the first storage circuit to be sequentially transmitted to the error correction circuit by sequentially activating the plurality of sub-read paths during a second sub-test section.