Semiconductor Test Circuit for Stacked Chip Electrical Validation
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Solution Overview
Problem
As semiconductor integration increases, ensuring proper electrical coupling and testing of multiple chips in a stacked configuration, such as through-silicon vias (TSV) and bump pads, becomes challenging due to complexity and the need for efficient testing methods.
Innovation Solution
A test circuit is implemented within the semiconductor apparatus that includes a pattern generator for generating internal test patterns, test units for transmitting and comparing these patterns across slices via pads, and a determining section to generate test determination values, enabling self-testing and external validation of electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple chips are arranged in a stacked configuration to increase integration degree, then the capacity of a single package is improved, but the complexity of electrical coupling and testing becomes worse
Solution Approach 1:
The test circuit is divided into multiple test units, each responsible for testing specific signal transmission elements. Each test unit includes a test pattern generation unit, a transmission unit, and a determination unit, allowing distributed testing across different chips in the stacked configuration. This segmentation reduces the overall testing complexity by dividing the large testing task into smaller, manageable units.
Solution Approach 2:
The test circuit enables self-testing capability where each chip can autonomously generate test patterns, transmit them through signal transmission elements, and determine the test results without requiring external test equipment for each individual chip. The determination unit automatically compares received test patterns with generated patterns to identify defects, allowing the system to self-diagnose and self-test.
2Reliability
If traditional external testing methods are used for multi-chip packages, then testing coverage is improved, but the time required for testing increases
Solution Approach 1:
Test patterns are generated and prepared in advance within each chip's test circuit before actual testing begins. The test pattern generation unit creates comprehensive test patterns that can be immediately transmitted and tested, eliminating the need for time-consuming external pattern generation during the testing process. This preliminary preparation significantly reduces overall testing time while maintaining comprehensive coverage.
Solution Approach 2:
The test circuit enables continuous testing operation where test patterns can be transmitted and processed without interruption between chips. The automated determination unit continuously compares received patterns with generated patterns and identifies defects in real-time, eliminating idle time between testing operations. This continuous testing approach maintains high reliability coverage while reducing total testing time.
Data Source
AI summary
A test circuit of a semiconductor apparatus includes a plurality of pads, a pattern generator configured to generate at least one internal test pattern in response to at least one pattern select signal, and a plurality of test units configured to transmit the at least one internal test pattern through the plurality of pads in response to a self test mode signal, and to compare the at least one test pattern received via the plurality of pads with the at least one generated internal test pattern and generate at least one test determination value based on the comparison.