Semiconductor Test Circuit for Leakage-Free Transistor Characterization

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Solution Overview

Problem

Current methods for measuring the operation current of transistors in semiconductor devices face challenges, particularly at high speeds, due to increased loading on data pads and inaccuracies caused by leakage when using Kelvin contact probes, which apply voltages not higher than ground voltage.

Innovation Solution

A semiconductor device with a test circuit comprising NMOS and PMOS transistors, switching elements, and monitoring pads, allowing for precise measurement of saturation currents by forming specific current paths and adjusting voltages to prevent leakage, enabling accurate detection of transistor characteristics without applying voltages higher than ground voltage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If Kelvin contact probes are used to measure transistor operation current, then measurement can be performed, but current leakage occurs and measurement accuracy deteriorates

Engineering Contradiction:
Improvetransistor operation current measurement accuracyVSAvoidcurrent leakage
Core Design Contradiction:
Measurement precisionVSObject-affected harmful factors

Solution Approach 1:

The patent introduces an intermediary measurement circuit between the Kelvin contact probes and the transistor. This circuit includes switching elements, resistors, and monitoring pads that mediate the measurement process, allowing accurate current measurement without direct high-voltage contact that causes leakage

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The measurement system is segmented into multiple functional components: voltage application path, current measurement path, and monitoring path. By separating these functions into distinct circuit segments with dedicated switching elements and monitoring pads, the system achieves accurate measurement while preventing leakage through controlled isolation

Inventive Principle:
Principle #1Segmentation

2Productivity

If high speed operation is required, then productivity increases, but loading on data pads increases causing measurement difficulties

Engineering Contradiction:
Improveoperating speedVSAvoiddata pad loading
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent adds a dedicated monitoring dimension by introducing separate monitoring pads and switching elements that operate independently from the data pads. This dimensional separation allows high-speed data operations to continue while simultaneous monitoring occurs through a different circuit path, avoiding the loading problem

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Measurement precision

If constant voltage is applied to transistors for current measurement, then operation current can be measured, but it is not practical for transistors arranged in various circuits

Engineering Contradiction:
Improveoperation current measurementVSAvoidapplicability to various circuit configurations
Core Design Contradiction:
Measurement precisionVSEase of operation

Solution Approach 1:

The patent employs dynamic switching elements that can reconfigure the measurement circuit based on the transistor's position and circuit configuration. The switching elements can dynamically connect different transistors to the monitoring pads, allowing the same measurement approach to work across various circuit configurations without requiring constant voltage application to all transistors simultaneously

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS11327112B2Semiconductor device for detecting characteristics of semiconductor element and operating method thereof
Publication Date: 2022.05.10 SK HYNIX INC
  • US11327112B2 patent drawing
  • US11327112B2 patent drawing
  • US11327112B2 patent drawing

AI summary

According to an embodiment, a semiconductor device comprises a first monitoring pad and a second monitoring pad; a test circuit including an NMOS transistor having a drain and source coupled between a first voltage terminal and a common node, a PMOS transistor having a drain and source coupled between the common node and a second voltage terminal, a first switching element having a first terminal coupled to the common node via a first resistor and a second terminal coupled to the first monitoring pad, and a second switching element having a third terminal coupled to the common node via a second resistor and a fourth terminal coupled to the second monitoring pad; and a test control circuit suitable for controlling the test circuit.