Semiconductor Test Device Internal Clock Generation
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Solution Overview
Problem
Conventional semiconductor test devices face challenges in achieving high-speed testing of semiconductor memory devices due to limitations in generating internal high-speed clock signals and data, leading to increased production costs and test times, especially at the wafer level where external clock and data dependencies restrict the number of chips that can be tested simultaneously.
Innovation Solution
A semiconductor test device that internally generates a high-speed clock signal and data, utilizing a clock generator, data generator, and data latch circuit to enable efficient testing by bypassing external clock and data dependencies, allowing for simultaneous testing of multiple chips at high speeds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If external clock and data are used for testing, then testing can be performed, but the number of chips that can be tested simultaneously is limited and test speed is restricted
Solution Approach 1:
The patent extracts the clock signal generation function from external equipment and implements it within the test device itself. The clock generator internally produces high-speed clock signals, eliminating the bottleneck of external clock provision and enabling simultaneous testing of multiple chips without external clock constraints
Solution Approach 2:
The test device becomes self-sufficient by internally generating both clock signals and test data. The data generator and clock generator work together to provide all necessary test inputs without external assistance, allowing the device to serve itself and multiple chips simultaneously at high speeds
2Productivity
If high-speed testing is implemented, then test efficiency increases, but the requirement for high-speed internal clock generation becomes critical
Solution Approach 1:
The clock generator is designed to pre-generate high-speed clock signals before actual testing begins. This preliminary preparation of clock signals ensures that when testing starts, the device is already ready to operate at maximum speed without waiting for external clock setup
Solution Approach 2:
The patent changes the operating parameters by implementing an internal clock generator that can produce higher frequency signals than external sources. This parameter change in clock generation capability directly enables high-speed testing while managing the complexity through integrated design
3Ease of manufacture
If wafer-level testing is performed, then production costs decrease, but the number of testing channels is limited
Solution Approach 1:
The test device achieves multi-functionality by internally generating clock signals and test data, allowing a single device to perform multiple testing functions simultaneously on multiple chips. This universality eliminates the need for separate external clock and data sources for each channel, effectively increasing the number of testing channels available at wafer-level
Data Source
AI summary
A semiconductor test device performs a test using a high-speed internal clock. The semiconductor test device includes a clock generator suitable for generating an internal clock in response to a test mode signal during a test mode, a data generator suitable for generating internal data in response to the internal clock, and a data latch circuit suitable for latching the internal data in response to the internal clock, and outputting the latched data to an internal logic circuit.