Semiconductor Test Controller Background Write Signal Toggling
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Solution Overview
Problem
Current semiconductor device testing processes are time-consuming and costly, particularly in detecting defective or failed parts during the probe test, which hampers the efficiency and reliability of semiconductor manufacturing.
Innovation Solution
A semiconductor device and system that includes a test controller for counting a read flag signal and toggling a data mask signal at specific activation times, enabling efficient detection of defective parts during a probe test by performing background write operations and reading/writing data in a cell array, thereby reducing test time and costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional testing processes are used for semiconductor devices, then testing can be performed, but the test time is excessive and costs are high
Solution Approach 1:
The patent applies preliminary action by performing background write operations to the cell array before the actual probe test. The test controller pre-loads reference data into the cell array during a background write phase, so that when the probe test begins, the comparison can immediately proceed without delay. This preliminary preparation eliminates the need to perform write operations during the critical test phase, significantly reducing overall test time.
Solution Approach 2:
The patent merges multiple functions into the test controller: it combines the data mask signal generation, read flag signal counting, background write operation control, and probe test execution into a single integrated controller. By consolidating these functions, the system eliminates the need for separate testing equipment and reduces the number of sequential operations required, thereby improving test speed and reducing costs.
2Reliability
If comprehensive testing is performed to ensure reliability, then defective parts can be detected, but the testing process becomes time-consuming and costly
Solution Approach 1:
The patent implements feedback through the read flag signal mechanism. The test controller monitors the read flag signal to determine when background write operations are complete and when the cell array is ready for probe testing. This feedback loop ensures that testing proceeds only when conditions are optimal, maintaining high detection accuracy while avoiding unnecessary delays. The counter circuit provides additional feedback by tracking the number of read operations, enabling precise control of the testing sequence.
Solution Approach 2:
The patent segments the testing process into distinct phases: a background write phase for pre-loading data, and a probe test phase for actual defect detection. By dividing the comprehensive testing into these segments, the system can perform thorough reliability checks during the background phase without impacting the speed of the critical probe test phase. This segmentation maintains high detection accuracy while improving overall test efficiency.
Data Source
AI summary
A semiconductor device and a system including the semiconductor device are disclosed, which relate to a technology for detecting a defective or failed part during a probe test of the semiconductor device. The semiconductor device includes a test controller configured to perform counting of a read flag signal during activation of a test signal and to control a data mask signal to be toggled at an N-th activation time of the read flag signal. The semiconductor device further includes a cell array configured to receive and store an output signal of the test controller through a data line during a write operation and to output the stored data to a test device during a read operation.