Semiconductor Test Data Grouping for Low-Current Parallel Testing

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Solution Overview

Problem

Existing semiconductor device testing apparatuses face challenges in efficiently testing multiple devices simultaneously due to high current consumption, leading to increased costs and complexity in programming and apparatus expense.

Innovation Solution

A semiconductor device testing apparatus that divides devices into groups based on current consumption, using test group identification signals to selectively write and execute test data, reducing the need for complex programming and expensive equipment.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a program consisting of test items with high current consumption and low current consumption is installed to test multiple devices, then the number of devices that can be simultaneously tested increases, but the program becomes complicated and the apparatus cost increases

Engineering Contradiction:
Improvenumber of devices tested simultaneouslyVSAvoidprogram complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments devices into multiple test groups based on their current consumption characteristics. Each group is assigned specific test items, allowing the testing apparatus to manage complexity through structured organization rather than complex programming. The test controller automatically selects and assigns test items based on device groupings, eliminating the need for complicated manual program configuration.

Inventive Principle:
Principle #1Segmentation

2Adaptability or versatility

If individual test items are instructed to each device through complex programming, then testing flexibility is improved, but the apparatus cost and programming expense increase

Engineering Contradiction:
Improvetesting flexibilityVSAvoidapparatus cost
Core Design Contradiction:
Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

The patent implements a universal testing framework where the test controller can accommodate multiple device types and test items through a standardized group-based architecture. The same testing apparatus can test different devices by simply changing the group configuration and test item selection, eliminating the need for expensive device-specific programming or multiple specialized apparatuses.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If test items with high current consumption are executed, then comprehensive testing coverage is achieved, but the total current consumption of the testing apparatus increases

Engineering Contradiction:
Improvetesting coverageVSAvoidtotal current consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent employs periodic action by sequentially executing test items for different device groups rather than simultaneously executing all test items for all devices. The test controller alternates between groups, allowing high current consumption test items to be performed on different devices at different time periods, thereby maintaining comprehensive testing coverage while reducing the peak total current consumption of the apparatus.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS20250349380A1Semiconductor device, semiconductor device testing apparatus and semiconductor device testing method
Publication Date: 2025.11.13 RENESAS ELECTRONICS CORP
  • US20250349380A1 patent drawing
  • US20250349380A1 patent drawing
  • US20250349380A1 patent drawing

AI summary

A semiconductor device includes a central processing unit (CPU), a memory, a test data input terminal that receive test data, a test group identification terminal that receive a test group identification signal, a test data input control unit that receives the test group identification signal through the test group identification terminal and generates a memory write enable signal for allowing the test data to be written into the memory based on the test group identification signal, and a memory write control circuit that generates test data write address and selects the test data received through the test data input terminal based on the memory write enable signal to transfer the test data selected and the test data write address to the memory, whereby a test with the test data in the memory is executed.