Semiconductor Test Data Storage Using Shared Pad Multiplexing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor device testing methods lack efficient mechanisms for data input and output operations, particularly in systems-in-package (SiP) and chip-on-chip (CoC) techniques, which hinder effective high-frequency data transmission and memory capacity enhancement.
Innovation Solution
A semiconductor device is designed with specific circuits for data input and output, including a test control circuit generating signals to manage data operations between pads and a memory cell array, enabling efficient data storage and retrieval during different operation periods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If micro-bump pads are used to improve data transmission speed, then data transmission speed is improved, but device complexity increases
Solution Approach 1:
The patent combines the test data input function and test data output function into a single pad structure. The pad can operate in different modes (input mode and output mode) depending on the operation period, eliminating the need for separate dedicated input and output pads. This merging approach maintains high-speed data transmission capability while reducing the overall number of pads required, thereby decreasing device complexity.
Solution Approach 2:
The pad is designed with multi-functionality to serve both as a test data input interface and a test data output interface. By incorporating control circuits that can switch the pad's operation mode based on timing signals, the same physical structure performs multiple functions. This universal design reduces the total pad count while maintaining the required data transmission performance.
2Ease of operation
If separate input and output pads are used for test data, then data input and output operations are simplified, but the number of pads increases
Solution Approach 1:
The patent merges the functionality of separate input pads and output pads into a single unified pad structure. During different operation periods, the same pad can be configured to receive test data or output test data through control signals. This approach maintains operational simplicity while significantly reducing the total number of pads required on the device.
Solution Approach 2:
The pad's function is made dynamic rather than static. Control circuits switch the pad's operational mode based on timing signals, allowing it to transition between input and output functions. This dynamic reconfiguration enables a single pad to replace what would traditionally require multiple dedicated pads, reducing device complexity while maintaining ease of operation.
3Reliability
If test data is stored in memory cell array during test operation, then testing capability is improved, but data transmission speed may be reduced
Solution Approach 1:
The patent implements periodic action by separating test operations into distinct time periods. During a first operation period, the pad operates in input mode to receive test data which is then stored in the memory cell array. During a second operation period, the same pad operates in output mode to retrieve and output the stored test data. This time-division multiplexing approach allows complete testing functionality while maintaining high-speed data transmission capability during each specific operation phase.
Solution Approach 2:
The patent applies preliminary action by storing test data in the memory cell array during the first operation period before the actual test evaluation begins. This preliminary storage phase allows the data to be prepared and organized, enabling high-speed retrieval and output during the subsequent second operation period without compromising the overall testing capability or speed.
Data Source
AI summary
A first data input circuit receives test data from a first pad to generate first input control data for generating cell input data stored in a memory cell array during a first operation period. A first data output circuit receives first output control data generated from cell output data outputted from the memory cell array to output the first output control data to an internal node coupled to a second pad during a second operation period.