Semiconductor Test Data Transfer via High-Speed Link
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Solution Overview
Problem
Existing techniques for system-level testing of semiconductor devices are inefficient due to increased complexity, requiring longer testing times and specialized automated test equipment, which limits testing after the device is installed in a final system and fails to simulate operational environmental conditions.
Innovation Solution
A method using a high-speed data transfer link and direct memory access to transfer test data and results directly between a host computer and a semiconductor device, enabling faster testing and in-system testing without specialized equipment, under actual operational conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ATE is used to transfer test data and results using dedicated test input/output pins or pads, then testing can be performed with specialized equipment, but testing time increases due to fewer available pins and increased complexity
Solution Approach 1:
The patent applies universality by enabling general-purpose input/output pins to serve dual functions: normal operational I/O during device operation and test data transfer during testing. This eliminates the need for dedicated test pins, allowing all pins to be used for testing without increasing pin count requirements, thereby reducing testing time while maintaining comprehensive testing capability
Solution Approach 2:
The patent uses copying by transferring test data and results through the high-speed data transfer link that replicates the operational communication interface. Instead of using separate dedicated test interfaces, the system copies the operational I/O pathway to also handle test data transfer, enabling faster testing without requiring additional specialized hardware
2Reliability
If ATE is used with dedicated test input/output pins, then testing can be performed at manufacturing, but testing cannot be performed after the device is installed in a final system
Solution Approach 1:
The patent enables the same general-purpose input/output pins to be used for both manufacturing testing and in-system testing. The pins serve multiple functions across different testing phases, allowing the device to be tested at manufacturing and continue to be tested after installation in the final system without requiring separate dedicated test interfaces
Solution Approach 2:
The patent implements dynamics by allowing the input/output pins to dynamically switch between operational mode and test mode. The pins adapt their function based on the testing phase, enabling seamless transition from manufacturing testing to in-system testing without hardware changes or additional dedicated test interfaces
3Ease of manufacture
If ATE performs manufacturing test outside the final system, then testing can be completed before deployment, but the test does not simulate actual operational environmental conditions
Solution Approach 1:
The patent applies preliminary action by performing manufacturing tests using the same general-purpose input/output pins and communication interfaces that will be used during actual operational testing. This preliminary testing is conducted under conditions that closely simulate future operational environments, ensuring test results correlate with actual device performance before deployment
Solution Approach 2:
The patent utilizes parameter changes by conducting tests under varying environmental conditions (temperature, voltage, frequency) that match the range of operational conditions. The testing system adjusts parameters such as clock frequency and voltage levels to simulate different operational scenarios, ensuring comprehensive validation before and during deployment
Data Source
AI summary
Techniques for testing semiconductor devices include a semiconductor device having a plurality of components, a test bus, and a test data transfer unit. The test data transfer unit receives, from a host computer, configuration information for performing a test of the semiconductor device, reads, via a high-speed data transfer link, test data associated with the test from memory of the host computer using direct memory access, sends the test data to the plurality of components via the test bus, causes one or more operations to be performed on the semiconductor device to effect at least a portion of the test, and after the one or more operations have completed, retrieves test results of the at least a portion of the test from the test bus and stores, via the high-speed data transfer link, the test results in the memory of the host computer using direct memory access.