Semiconductor Test Decoder Using Post-FEOL Logic Cells
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Solution Overview
Problem
Current methods for testing semiconductor devices are inefficient in measuring the current-voltage characteristics of a large number of transistors, particularly during the Front End Of Line (FEOL) process, which hinders the detection of defects and yield improvement in semiconductor manufacturing.
Innovation Solution
A method and semiconductor device that form a decoder using existing logic cells and elements after the FEOL process, connecting it to transistors, and using pads to select and measure the electrical characteristics of individual transistors, allowing for efficient testing of multiple transistors on a chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If three pads are used to measure DC characteristic of a transistor, then the measurement can be performed, but the number of transistors that can be tested is limited
Solution Approach 1:
The chip is divided into multiple regions with each region containing a subset of transistors that can be independently selected and measured. The selection logic segments the transistor testing into manageable groups, allowing systematic testing of large numbers of transistors through sequential selection rather than requiring all transistors to be tested simultaneously
Solution Approach 2:
Selection logic circuits are introduced as intermediary components between the pads and the transistors. These selection logic circuits receive selection signals through the pads and activate specific transistors for measurement, enabling the three pads to control and measure many more transistors than the traditional one-to-one mapping approach
2Device complexity
If selection logic is formed using existing logic cells and elements after FEOL process, then device complexity is reduced, but manufacturing process complexity increases
Solution Approach 1:
The selection logic is constructed using existing logic cells and elements that are already present on the chip after the FEOL process. By utilizing pre-existing structures rather than requiring entirely new fabrication steps, the approach reduces overall manufacturing complexity while still achieving the functionality of transistor selection
Solution Approach 2:
The methodology repurposes existing logic cells and elements that would otherwise remain unused or serve different functions. By recovering and reconfiguring these existing structures as selection logic, the patent avoids adding significant manufacturing complexity while achieving device selection capability
Data Source
AI summary
Provided is a method for testing a plurality of transistors of a semiconductor device. The method includes forming a plurality of elements or a plurality of logic using a Front End Of Line (FEOL) process, forming a selection logic using at least one of the plurality of elements or the plurality of logic cells, connecting the selection logic and the plurality of transistors, forming a pad for connecting an input terminal of the selection logic and drain or source terminals of the plurality of transistors, and sequentially selecting the plurality of transistors using the selection logic and measuring an electrical characteristic of selected transistors among the plurality of transistors.