Semiconductor Test Circuit for Resistive and Leakage Defect Detection

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Solution Overview

Problem

Existing semiconductor devices face challenges in accurately and rapidly detecting defects such as resistive and leakage current defects in circuit components like metal lines, necessitating improved test circuits for reliability verification.

Innovation Solution

A test circuit that adjusts charging and discharging conditions through varying current quantities or reference voltages during different measurement intervals, coupled with a counting mechanism to generate and output test result information for defect detection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a fixed charging current quantity is used during test measurement, then the test circuit operation is simple, but the defect detection accuracy is insufficient

Engineering Contradiction:
Improvedefect detection accuracyVSAvoidtest circuit complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent applies dynamics by making the charging current quantity variable rather than fixed. The test core dynamically adjusts the charging current quantity between different measurement intervals, changing from a first value during a first measurement interval to a second value during a second measurement interval. This dynamic adjustment enables the test circuit to detect defects with higher accuracy while managing complexity through controlled variability.

Inventive Principle:
Principle #15Dynamics

2Reliability

If measurement is performed with single test condition, then the measurement process is fast, but the reliability of defect detection is reduced

Engineering Contradiction:
Improvedefect detection reliabilityVSAvoidmeasurement time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent implements periodic action by performing measurements under multiple different test conditions across different measurement intervals. The test core alternates between different charging current quantities (first value and second value) during different measurement intervals, allowing the system to gather comprehensive defect detection data reliably while managing measurement time through structured periodic testing.

Inventive Principle:
Principle #19Periodic action

3Measurement precision

If multiple measurement intervals with different parameters are used, then defect detection accuracy improves, but the control complexity increases

Engineering Contradiction:
Improvedefect measurement accuracyVSAvoidtest control ease
Core Design Contradiction:
Measurement precisionVSEase of operation

Solution Approach 1:

The patent applies self-service by enabling the test core to automatically manage multiple measurement intervals with different parameters without requiring external intervention. The test core autonomously changes the charging current quantity between measurement intervals, performs the appropriate measurements, and transitions between test conditions, thereby improving defect measurement accuracy while maintaining ease of operation through automated control.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS12609178B2Test circuit and semiconductor memory system including the test circuit
Publication Date: 2026.04.21 SK HYNIX INC
  • US12609178B2 patent drawing
  • US12609178B2 patent drawing
  • US12609178B2 patent drawing

AI summary

A test circuit including a test core configured to set a charging current quantity as a first value and perform charging and discharging on a test node of a test target circuit during a first measurement interval and configured to change the charging current quantity from the first value to a second value and perform charging and discharging on the test node during a second measurement interval, and an operation circuit configured to generate a first counting value by counting a clock signal during the first measurement interval, generate a second counting value by counting the clock signal during the second measurement interval, generate the results of an operation of the first counting value and the second counting value as operation results, and output at least one of the first counting value, the second counting value, and the operation results as test result information.