Semiconductor Test Device for Contact Bridge Diagnosis
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Solution Overview
Problem
The increasing integration density of semiconductor memory devices leads to smaller metal contacts, resulting in inaccurately patterned contacts and increased failures due to electrical connections between adjacent shared contacts, known as bridges, which are difficult to diagnose accurately.
Innovation Solution
A test device and semiconductor integrated circuit device with specific layouts and current detection parts in test regions to determine if current flows between nodes, allowing for the measurement of leakage current and identification of bridge causes, including the use of first and second test regions with distinct layouts and current detection parts to isolate issues in static memory cell regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If integration density of semiconductor memory devices is increased, then memory capacity and bandwidth are improved, but metal contact size decreases leading to inaccurate patterning and increased contact failures
Solution Approach 1:
The patent divides the test structure into multiple separate test regions (first test region and second test region) with distinct layouts. Each region tests specific components independently - the first region tests shared contacts while the second region tests other memory cell components. This segmentation allows accurate identification of whether failures originate from contact patterning issues or other manufacturing defects, resolving the contradiction by enabling precise fault isolation despite reduced contact sizes.
2Reliability
If adjacent shared contacts are electrically connected (bridge formation), then current flows between nodes, but the cause of current flow cannot be accurately determined
Solution Approach 1:
The patent creates segmented test regions where the first test region contains shared contacts connected to first nodes, and the second test region contains memory cell components connected to second nodes. By applying voltages to different node pairs and measuring current flow in each region separately, the system can precisely determine whether current flow is caused by bridges between shared contacts (detected in first region) or other defects (detected in second region), thereby improving measurement precision for bridge detection.
Solution Approach 2:
The patent introduces isolation regions as intermediary elements between adjacent shared contacts and active regions. These isolation regions prevent unintended electrical connections and serve as mediators to isolate specific test paths. By controlling which regions are electrically connected through these intermediaries, the system can accurately attribute current flow to specific defect types, resolving the ambiguity in bridge detection.
3Measurement precision
If current flow between nodes is detected, then bridge occurrence can be identified, but the specific cause (short-circuit location) cannot be determined
Solution Approach 1:
The patent segments the measurement system into two independent test regions with separate voltage application and current measurement paths. The first test region measures current between first nodes to detect shared contact bridges, while the second test region measures current between second nodes to detect other defects. This segmentation transforms a single ambiguous measurement into two distinct measurements, making it possible to precisely identify the location and cause of defects based on which region exhibits current flow.
Data Source
AI summary
A test device includes a semiconductor substrate having a first test region and a second test region defined thereon, wherein a layout of the first test region includes first active regions separated from each other by isolation regions in the semiconductor substrate, second active regions formed between the first active regions, first gate lines formed on the semiconductor substrate, wherein each of the first gate lines has a first end adjacent to one of the first active regions and a second end adjacent to an end of one of the second active regions, respectively, first shared contacts each formed over a respective one of the second ends of the first gate lines and an upper part of one of the first active regions, and first nodes formed on the first shared contacts to be electrically connected to the first shared contacts, respectively.