Semiconductor Test Device Segmentation for Contact Bridge Detection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in semiconductor integrated circuit devices, particularly in SRAM cells, is the difficulty in accurately patterning smaller metal contacts, which can lead to inferior or defective contacts and potential short circuits due to bridges between shared contacts, making it hard to determine whether bridges are formed between adjacent shared contacts.
Innovation Solution
A test device and semiconductor integrated circuit design with defined test regions and elements, including primary and secondary test regions, test gate lines, and nodes, allows for the application of voltage to detect current flow between test shared contacts and nodes, enabling accurate determination of short circuits and improving productivity by isolating the source of the issue.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the size of metal contacts is reduced to increase integration, then the memory cell size becomes smaller and integration increases, but the patterning accuracy deteriorates and defective contacts with bridges are formed
Solution Approach 1:
The test structure is divided into multiple regions: a first test region with shared contacts and gate lines, a second test region with shared contacts but without gate lines, and a third test region without shared contacts. This segmentation allows independent testing of different failure modes - bridges between shared contacts, short circuits between gate lines and active regions, and other defects - enabling precise identification of defect sources despite reduced contact size
Solution Approach 2:
Isolation regions are introduced as intermediary structures between adjacent active regions. These isolation regions serve as physical barriers that prevent bridge formation between shared contacts while maintaining the reduced contact size needed for high integration. The isolation regions act as mediators that resolve the contradiction between small contact size and patterning accuracy
2Measurement precision
If voltage is applied to nodes connected to adjacent shared contacts to detect bridges, then bridge detection is enabled, but false positives occur due to other short circuit paths
Solution Approach 1:
The test methodology segments the detection process into three distinct test regions, each testing for specific failure modes. By applying voltage to nodes in different regions and comparing results, the system can isolate whether current flow is due to bridges between shared contacts (first region), short circuits involving gate lines (second region), or other defects (third region). This segmented approach eliminates false positives by identifying the specific source of short circuits
Solution Approach 2:
The test structure incorporates feedback through comparative analysis of test results from three different regions. By comparing the electrical characteristics measured in each region against expected values and against each other, the system provides feedback that enables accurate identification of defect types. The feedback mechanism distinguishes between bridge defects and other short circuit conditions, improving detection reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enables accurate measurement of short circuits in test regions, reflecting the SRAM cell region's conditions, thus enhancing the productivity of semiconductor integrated circuit devices by clearly identifying whether short circuits are caused by test shared contacts or nodes.
Implementation Method 1
A voltage may be applied to the nodes which may cause a current to flow from one node to another
Data Source
AI summary
Test devices and integrated circuits with improved productivity are provided. In accordance with example embodiments, a test device may include a first test region with a first test element and a second test region with a second test element defined on a semiconductor substrate. The first test element may include a pair of first secondary test regions in the semiconductor substrate and a pair of first test gate lines. One of the first test gate lines may overlap one of the first secondary test regions and the other first test gate line may overlap the other first secondary test region. The second test element may include structures corresponding to the first test element except the second test element does not include structures corresponding to the pair of first secondary test regions and the pair of first test gate lines.