Semiconductor Test Circuit Using Dual Random Number Generation
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Solution Overview
Problem
Existing semiconductor device test methods using linear feedback shift registers face challenges such as increased test time due to longer clock periods and difficulty in controlling data rate changes on scan chains, especially when clock signals are not blocked.
Innovation Solution
A semiconductor device configuration that includes a first random number generation circuit, a second random number generation circuit, and a random number control circuit to manage clock periods and data rate changes, allowing for efficient test pattern generation without extending clock periods or blocking clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If the clock period of the scan chain is made longer to match the pattern generator clock period, then timing alignment is improved, but the test time increases due to more clocks being required
Solution Approach 1:
The patent divides the random number generation function into two separate circuits: a first random number generation circuit that operates at the pattern generator clock frequency, and a second random number generation circuit that operates at the scan chain clock frequency. This segmentation allows each circuit to operate independently at its optimal frequency without requiring clock period matching, thereby resolving the contradiction between timing alignment and test time.
Solution Approach 2:
The patent introduces a random number control circuit as an intermediary that uses random numbers from the second circuit to modify random numbers from the first circuit. This intermediary structure enables the two independently operating random number generation circuits to work together effectively, maintaining timing alignment through controlled interaction rather than synchronized clock periods.
2Adaptability or versatility
If the rate of change of data on the scan chain is arbitrarily set, then test pattern diversity is improved, but external clock control is required which reduces design flexibility
Solution Approach 1:
The patent implements self-service by having the random number control circuit automatically control the inversion logic circuit using random numbers generated by the second random number generation circuit. This self-controlled mechanism achieves arbitrary data rate changes on the scan chain without requiring external clock control, thereby maintaining design flexibility while improving test pattern diversity.
Solution Approach 2:
The patent introduces dynamic control by using randomly generated values to dynamically adjust the inversion logic circuit's operation. This dynamic approach allows the data rate of change on the scan chain to vary arbitrarily based on random patterns rather than fixed external clock control, achieving adaptability without sacrificing design flexibility.
3Speed
If the clock signal is blocked to stop random number generation, then data rate control is achieved, but timing design and layout become more difficult
Solution Approach 1:
The patent extracts the clock signal blocking function by replacing it with a random number-based control mechanism. Instead of blocking the clock signal to stop random number generation, the system uses the second random number generation circuit to generate control values that selectively inhibit or enable the first random number generation circuit's output. This extraction eliminates the need for clock blocking while achieving the same data rate control effect, thereby reducing timing design complexity.
Data Source
AI summary
A semiconductor device includes a test target circuit; scan chains that enable scanning of the test target circuit; a first random number generation circuit that forms test patterns supplied to the scan chains; a second random number generation circuit that is provided separately from the first random number generation circuit; and a random number control circuit that uses the random numbers generated by the second random number generation circuit to change the random numbers generated by the first random number generation circuit. In a test of the semiconductor device, since a period of a clock of a scan chain does not need to be longer than that of a clock of a pattern generator, the number of clocks of the pattern generator needed for a test can be prevented from increasing. Accordingly, a test time can be prevented from increasing.