Semiconductor Test System Interpreting Source Code for Multi-ISA Execution
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Solution Overview
Problem
The semiconductor industry faces inefficiencies in maintaining source code for test devices due to the need for multiple test devices, each using different programming languages, leading to time-consuming and error-prone updates.
Innovation Solution
A semiconductor test method and system that interprets source code to generate interpreted code, allowing multiple test apparatuses to perform tests using either compiled or interpreted languages, with a processor updating and compiling the code to execute machine code for consistent testing across different devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple different test devices are purchased to test the same characteristic of semiconductor products, then throughput is increased, but source code maintenance becomes more complex and error-prone
Solution Approach 1:
The patent implements a universal test system architecture where a single processor can execute multiple different test programs written in different programming languages. The processor includes multiple instruction set architectures (ISAs) that support different language families (CISC, RISC, stack-based), allowing one test device to perform functions previously requiring multiple specialized devices. This universality resolves the contradiction by enabling one device to replace many while maintaining the ability to handle diverse test requirements.
Solution Approach 2:
The patent introduces an intermediary layer in the form of a unified processor architecture that mediates between different programming languages and the underlying hardware. The processor translates and executes instructions from multiple language families through a common instruction set architecture, acting as a mediator that allows diverse test programs to run on a single platform without requiring separate compilation and execution environments for each language.
2Adaptability or versatility
If source code is modified separately for every test device when updating test functions, then each device can be customized, but the update process becomes time-consuming and error-prone
Solution Approach 1:
The unified processor architecture enables a single source code base to be compiled into multiple instruction set formats simultaneously. When a test function needs updating, the modified source code is compiled once and can be executed on all test devices through the processor's multiple ISAs, eliminating the need for separate modifications for each device while preserving customization capabilities.
Solution Approach 2:
The patent merges the previously separate compilation and execution processes for different programming languages into a unified process. The processor combines multiple instruction set architectures into a single execution engine that can handle different language families, allowing source code updates to be applied once across all test devices rather than separately for each device.
3Ease of manufacture
If multiple programming languages are used across different test devices, then each device can optimize for specific test types, but code portability and consistency are reduced
Solution Approach 1:
The processor implements multiple instruction set architectures (CISC, RISC, stack-based) within a single device, enabling it to execute programs written in different programming language families. This universal capability allows source code to be ported across different test devices without modification, as the processor can adapt to execute the code in its native instruction set format while maintaining optimization benefits.
Solution Approach 2:
The patent changes the parameter of instruction set architecture from a fixed, device-specific configuration to a dynamic, multi-ISA configuration within a single processor. This allows the same physical device to change its operational parameters to match the requirements of different programming languages, achieving both optimization for specific test types and code portability simultaneously.
Data Source
AI summary
The present disclosure provides a semiconductor test method. The semiconductor test method includes the operations of: receiving a source code written in an interpreted language; and performing, by a first test apparatus, a first test on a device under test (DUT) based on the source code. The operation of performing, by the first test apparatus, the first test on the DUT based on the source code includes the operations of: interpreting, by a processor, the source code to generate a first interpreted code; and performing the first test on the DUT according to the first interpreted code. The first test apparatus is configured to execute the first interpreted code written in a first language.