Semiconductor Test Structure Array With Isomorphic Unit Cells
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Solution Overview
Problem
In CMOS logic processes, the variability of circuit performance and product yield is exacerbated by lithographic proximity variations and parasitic resistance issues in traditional test structure arrays, which limit the number of test devices that can be accommodated and hinder accurate measurements due to non-linear characteristics and excessive background leakage.
Innovation Solution
A semiconductor test structure array with isomorphic unit cells, each containing a device under test (DUT) and equipped with an access-control circuitry comprising four identical controlled transmission gates (CTGs), allowing for addressable and multiplexed access to DUTs while minimizing parasitic resistance effects through Kelvin sensing and ensuring operation in the linear region of transmission gates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional test structure arrays are used in scribe lines, then space utilization is efficient, but the number of test devices that can be accommodated is limited
Solution Approach 1:
The patent transitions from one-dimensional scribe line placement to two-dimensional array organization, allowing test devices to be arranged in rows and columns across the wafer surface. This dimensional expansion dramatically increases the number of test devices that can be accommodated within the same physical space, resolving the contradiction between quantity and area.
Solution Approach 2:
The patent creates a universal test vehicle design where a single array structure can accommodate multiple types of test devices (transistors, capacitors, resistors, etc.) through standardized unit cells. This multi-functional approach allows the same physical infrastructure to support diverse testing needs, increasing effective device quantity without proportionally increasing space requirements.
2Quantity of substance
If multiplexed cell access is implemented to increase device capacity, then more test devices can be accessed through limited probe pads, but parasitic resistance and non-linear characteristics degrade measurement accuracy
Solution Approach 1:
The patent divides the test array into independently addressable unit cells, each with its own access-control circuitry containing transmission gates. This segmentation allows selective activation of individual cells or groups of cells during testing, reducing the total number of simultaneously active multiplexing switches in the signal path and thereby minimizing cumulative parasitic resistance effects.
Solution Approach 2:
The patent introduces transmission gates as intermediary switching elements with controlled resistance characteristics. These gates act as mediators between the probe pads and the test devices, providing a known and controllable resistance path that can be compensated for or calibrated, thus maintaining measurement accuracy despite the presence of multiplexing structures.
3Adaptability or versatility
If each unit cell has different control circuits to accommodate various test devices, then device versatility is improved, but design complexity and manufacturing difficulty increase substantially
Solution Approach 1:
The patent implements a universal unit cell design where each cell contains identical access-control circuitry with transmission gates that can be programmed or configured to access different types of test devices. This standardized interface approach allows the same control circuit structure to handle diverse device types through configuration rather than hardware variation, maintaining versatility while dramatically reducing design and manufacturing complexity.
Data Source
AI summary
This invention discloses a semiconductor test structure array comprising a plurality of unit cells for containing devices under test (DUT) arranged in an addressable array, and an access-control circuitry within each unit cell for controlling accesses to one or more DUTs, wherein the access-control circuitry comprises at least four identical controlled transmission gates (CTGs), and a plurality of the access-control circuitries are isomorphic.