Semiconductor Integrated Circuit Test Parameter Latch and Selection
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Solution Overview
Problem
In semiconductor integrated circuit device testing, changing a bit with a fixed value for a specific address requires repeated trimming processes, leading to increased testing time and costs due to the overwrite of previously trimmed parameters.
Innovation Solution
A semiconductor integrated circuit device with a latch circuit and selection circuit that allows only the bit of a parameter with a fixed value to be changed without overwriting optimally trimmed bits, using a mask signal to control the selection circuit and prevent parameter overwrite.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If test parameter data is changed by modifying a bit with a fixed value for a specific address, then the parameter with fixed value can be adjusted, but the previously trimmed parameter bit is deleted together with the change, requiring repeated trimming processes
Solution Approach 1:
The patent divides the test parameter data into two distinct parts: a trimmed parameter bit that stores optimized values and a fixed value bit that stores constant data. This segmentation allows independent modification of the fixed value bit without affecting the trimmed parameter bit, preventing unnecessary re-trimming and reducing testing time while maintaining parameter adjustment flexibility
Solution Approach 2:
The patent introduces a mask signal as an intermediary control mechanism. The mask signal selectively enables or disables the update operation for different bits of test parameter data. By setting the mask signal to preserve the trimmed parameter bit while allowing changes to the fixed value bit, the system achieves both parameter adjustment and time efficiency without direct bit conflict
2Manufacturing precision
If repeated trimming processes are performed for the same address, then the parameter can be re-optimized, but the testing time increases significantly
Solution Approach 1:
The patent performs the trimming operation once during the initial test and stores the optimized value in the trimmed parameter bit. The mask signal is then configured to preserve this pre-optimized value during subsequent tests, eliminating the need for repeated trimming processes and significantly improving testing efficiency while maintaining parameter optimization
Solution Approach 2:
The patent discards the unnecessary re-trimming operations by using the mask signal to protect the already-optimized trimmed parameter bit. The system recovers from the potential loss of optimization by automatically preserving the trimmed value, thereby maintaining manufacturing precision without the time cost of repeated trimming
Data Source
AI summary
A semiconductor integrated circuit device related to an embodiment of the present invention includes an address register which includes an internal selection circuit connected with a control circuit, a signal generation instruction circuit which instructs the control circuit so that a predetermined internal control signal is generated, a latch circuit, a plurality of which are arranged corresponding to a number of bits of test parameter data, the latch circuit latching test result data which is provided from the data program/read circuit and outputting the test result data to the selection circuit and externally, the control circuit generating an internal control signal which activates the selection circuit at a timing at which a fixed value data of the test parameter data is changed, and the selection circuit controlling a test so that a fixed value data of the test parameter data is changed.