Semiconductor Device Test Mode for Leakage Current Screening
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Solution Overview
Problem
The increasing integration level in semiconductor devices using vertical-type cell transistors leads to increased capacitance between word lines, resulting in defective cells due to passing gate and neighbor gate effects, which prolong test times and reduce detection capability, especially in sub 100 nm technology with recess gates.
Innovation Solution
A semiconductor device and method that equalizes bit lines to ground voltage during a test mode, simultaneously enables even and odd word lines, and stops the sense amplifier operation to apply stress and screen passing gate and neighbor gate effects efficiently, reducing test time and improving detection capability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the tRAS time is increased to screen passing gate and neighbor gate effects, then the detection capability is improved, but the test time is extended
Solution Approach 1:
The patent applies preliminary action by performing stress testing of passing gate and neighbor gate effects during the precharge operation phase, before the main read operation begins. This allows defective cells to be identified early in the test sequence without extending the overall test time, as the stress testing is conducted in parallel with the normal precharge process.
Solution Approach 2:
The patent implements periodic action by incorporating multiple test cycles that alternately activate even and odd word lines in a systematic sequence. This periodic activation pattern allows comprehensive screening of all cells through repeated cycles of stress application and detection, improving detection capability while maintaining efficient test timing through structured repetition.
2Device complexity
If only one word line is enabled per active command, then the device complexity is reduced, but the screening efficiency of passing gate and neighbor gate effects is deteriorated
Solution Approach 1:
The patent applies segmentation by dividing the word line activation into two distinct phases: a first active command that enables only even word lines, and a second active command that enables only odd word lines. This segmented approach allows systematic screening of passing gate and neighbor gate effects for all cells through coordinated activation of specific word line groups, improving screening efficiency while maintaining manageable control complexity through structured division of the testing task.
Data Source
AI summary
A semiconductor device and a method for testing the same are disclosed, relating to a technology for simultaneously screening an off-leakage-current fail caused by a passing gate effect and a neighbor gate effect. The semiconductor device includes a memory cell configured to read and write data; a sense amplifier configured to sense and amplify cell data received from the memory cell through a pair of bit lines; a bit line precharge unit configured to equalize the pair of bit lines to a level of a ground voltage in response to a bit line equalization signal; a precharge voltage generator configured to provide the ground voltage to the bit line precharge unit during a test mode; and a test controller configured to, during the test mode, maintain an activation state of the bit line equalization signal during a test mode period, and control the sense amplifier to be deactivated.