Semiconductor Test Mode Control Unit for Seamless Mode Transition
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Solution Overview
Problem
Conventional semiconductor integrated circuits require increased test time due to the need to exit and re-enter test modes, which affects production throughput, as they cannot simultaneously inactivate test mode signals during mode transitions.
Innovation Solution
A semiconductor integrated circuit with a test mode control unit that selectively inactivates activated test mode signals using predetermined test mode signals as a reset signal, allowing for automatic conversion between concurrent and current test modes without disconnecting the test mode state.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If concurrent test modes are executed simultaneously using external reset signals, then test coverage is improved, but test time increases due to mode exit requirements
Solution Approach 1:
The test mode control unit automatically generates reset signals using its own internal test mode signals, eliminating the need for external reset signals. This self-service mechanism allows the circuit to manage mode transitions internally without time-consuming external interventions, resolving the contradiction between test mode flexibility and test time efficiency
Solution Approach 2:
The circuit prepares reset signals in advance by utilizing test mode signals before mode transitions are needed. By having reset signals ready through preliminary action, the circuit可以避免 delays associated with external reset signal generation, thus reducing test time while maintaining concurrent test capabilities
2Device complexity
If current test mode is used to execute single test modes sequentially, then test mode control is simplified, but total test time increases
Solution Approach 1:
The test mode control unit serves multiple functions: it generates test mode signals for concurrent tests, generates reset signals for mode transitions, and maintains test state continuity. This multi-functionality eliminates the need for separate external reset signal mechanisms, simplifying the overall control structure while enabling both concurrent and sequential test modes without increasing total test time
3Adaptability or versatility
If external reset signals are used to manage test mode transitions, then mode switching capability is improved, but production throughput decreases
Solution Approach 1:
The invention extracts the reset signal generation function from external sources and relocates it within the test mode control unit itself. By taking out the external reset signal dependency and embedding the generation capability internally, the circuit achieves fast mode transitions that do not interrupt test flow, thereby maintaining high production throughput while preserving mode switching capability
Data Source
AI summary
A semiconductor integrated circuit capable of controlling test modes without stopping testing of the semiconductor integrated circuit is presented. The semiconductor integrated circuit includes a test mode control unit configured to produce, in response to address decoding signals, a plurality of test mode signals of a first group and a plurality of test mode signals of a second group. The test mode control unit selectively inactivates the test mode signals of the first group by providing a reset signal using the test mode signals of the second group. Therefore, the testing time of the semiconductor integrated circuit can be reduced by inactivating the previous test mode using the reset signal and by executing a new test mode without disconnecting the test mode state.