Semiconductor Test Apparatus Noise Injection for Voltage Resistance

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing semiconductor test apparatuses cannot effectively check resistance characteristics against variations in pulse-like power supply voltages, particularly impulse noise, which is crucial for modern semiconductor devices operating with reduced voltages.

Innovation Solution

A semiconductor test apparatus that includes a voltage source, a decision processor, and a noise generator capable of superimposing impulse-like or periodic pulse-like noise voltages on the power supply to the Device Under Test (DUT) during a test sequence, allowing for the evaluation of resistance characteristics against these voltage variations. The noise generator can synchronize with the DUT's clock signal and adjust noise amplitude independently, enabling precise testing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a power supply voltage is fixedly varied while the test pattern is being executed, then the resistance characteristics against power supply voltage changes can be checked, but the resistance characteristics against pulse-like noise cannot be checked

Engineering Contradiction:
Improveresistance characteristics against power supply voltage changesVSAvoidability to check resistance against pulse-like noise
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent applies periodic action by superimposing periodic pulse-like noise voltages on the power supply voltage during test execution. The noise generator creates periodic disturbances at specific frequencies and duty cycles, allowing the system to evaluate resistance characteristics against pulsed voltage variations while maintaining continuous test operation.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The patent implements dynamics by making the noise voltage parameters adjustable and variable during testing. The system can dynamically change noise amplitude, frequency, and timing to simulate different pulse-like noise conditions, enabling versatile testing of resistance characteristics under various transient voltage scenarios.

Inventive Principle:
Principle #15Dynamics

2Measurement precision

If the noise voltage amplitude is increased to detect weak circuit blocks, then the measurement precision improves, but the device complexity increases

Engineering Contradiction:
Improvedetection precision of weak circuit blocksVSAvoidcomplexity of noise generator and control system
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent applies parameter changes by allowing independent adjustment of noise voltage amplitude, frequency, and timing parameters. The system modifies these electrical parameters to optimize detection precision for different circuit conditions without requiring complex hardware changes, achieving high measurement precision through flexible parameter control.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent implements feedback by using test results to identify weak circuit blocks and then adjusting noise voltage parameters to further investigate specific addresses. The system feeds back failure information to refine subsequent testing, improving detection precision through iterative parameter optimization based on observed circuit responses.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS8433990B2Semiconductor test apparatus and test method
Publication Date: 2013.04.30 ADVANTEST CORP
  • US8433990B2 patent drawing
  • US8433990B2 patent drawing
  • US8433990B2 patent drawing

AI summary

In a semiconductor test apparatus, a voltage source generates a power supply voltage to be supplied to a DUT. A decision processor makes the DUT execute a predetermined test sequence. A noise generator superimposes a periodic pulse-like noise voltage on the power supply voltage to be supplied to the DUT, while the test sequence is being executed. The noise generator superimposes a noise voltage synchronized with a clock signal to be supplied to the DUT.