Semiconductor Test Pad Central Placement for Area Reduction
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Solution Overview
Problem
The increasing power consumption and miniaturization of semiconductor devices lead to difficulties in securing stable power supply and circuit operation, particularly during wafer screening, due to increased wire resistance and chip area, resulting in higher costs and longer development times.
Innovation Solution
A semiconductor device with external connection pads and test pads arranged in a central region of the chip, reducing the need for periphery test pads, which decreases chip area and power-supply voltage drop, while maintaining stable screening capabilities for high-speed and large-scale circuits, and improving manufacturing efficiency and yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If test pads are arranged on the periphery of the chip, then screening in wafer state is enabled, but chip area increases
Solution Approach 1:
The patent moves test pads from the traditional periphery arrangement to the central region of the chip, utilizing the previously underutilized central area. This dimensional repositioning allows test functionality to be integrated without increasing the chip's external footprint, effectively using the central void space for testing purposes.
Solution Approach 2:
The central region of the chip is given dual functionality: it serves both as a space for power supply distribution and as a location for test pad arrangement. This multi-functional use of the central region eliminates the need for dedicated periphery test pads, thereby reducing overall chip area while maintaining screening capabilities.
2Reliability
If wire length is reduced by arranging area pads, then power supply stability is improved, but chip area increases
Solution Approach 1:
The patent implements local power supply optimization by placing test pads in the central region close to the power supply source. This local arrangement reduces the wire length specifically for power delivery to test structures, improving power supply stability without requiring area pads across the entire chip surface.
3Measurement precision
If probe resistance is reduced during wafer screening, then measurement accuracy is improved, but requires additional chip area for test pads
Solution Approach 1:
By relocating test pads from the periphery to the central region, the patent minimizes the distance between probe contact points and the underlying circuit structures. This reduces probe resistance and improves measurement accuracy during wafer screening, while the central location ensures this is achieved without expanding chip area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces chip area and power-supply voltage drop, enabling stable screening and shorter development times, while increasing yield and reliability in the manufacturing process, and reducing chip costs by effectively utilizing pad regions.
Implementation Method 1
a plurality of external connection electrodes each formed on a corresponding one of the external connection pads, the external connection electrodes being for connecting the external connection pads and an outside of the semiconductor device
Data Source
AI summary
A semiconductor device according to one embodiment of this invention includes: a semiconductor chip; a plurality of external connection pads and a plurality of first test pads, both of which are formed in a central region of a top surface of the semiconductor chip; a plurality of external connection electrodes each formed on a corresponding one of the external connection pads, the external connection electrodes being for connecting the external connection pads and an outside of the semiconductor device.