Semiconductor Test Pad Structure for Flat Probe Wafer Testing

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Solution Overview

Problem

Current wafer testing methods using needle probe tips are inefficient due to high precision requirements, short lifespan, and marking issues on test pads, while flat probe tips are limited to soft materials and cannot be used in large test areas.

Innovation Solution

The method involves forming a seed layer over test pads on IC dies, followed by a sacrificial soft metallic material like tin, allowing flat probe tips to perform tests without marking the pads, and subsequent removal of the sacrificial material for downstream processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If needle probe tips are used for wafer testing, then measurement precision and reliability are improved, but device complexity and manufacturing cost increase, and the probe tips have shorter usable life

Engineering Contradiction:
Improvetest measurement precisionVSAvoidprobe card complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent employs disposable probe tips that are inexpensive to manufacture and replace. These probe tips are designed to be used once or limited times and then discarded, eliminating the need for complex maintenance and calibration systems. The low cost allows the system to use simple, replaceable tips rather than expensive, durable ones, directly resolving the contradiction between measurement precision and device complexity.

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

Solution Approach 2:

The probe tips are pre-positioned and pre-calibrated during probe card assembly before actual testing begins. This preliminary setup ensures measurement precision is built into the system architecture rather than requiring complex real-time adjustment mechanisms during testing, thereby reducing device complexity while maintaining precision.

Inventive Principle:
Principle #10Preliminary action

2Measurement precision

If needle probe tips are used for wafer testing, then measurement precision is improved, but loss of time increases due to frequent replacement and maintenance

Engineering Contradiction:
Improvetest measurement precisionVSAvoidprobe replacement time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

By using inexpensive disposable probe tips, the system eliminates time-consuming maintenance and calibration procedures. The low cost enables a strategy where probe tips are quickly replaced rather than repaired, significantly reducing the loss of time associated with probe card maintenance while maintaining measurement precision through consistent factory calibration of each new tip.

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

Solution Approach 2:

The patent implements a rapid replacement protocol where depleted probe tips are quickly swapped with pre-prepared spare tips. This skipping of complex maintenance procedures and rushing through the replacement process minimizes downtime, directly addressing the time loss issue while preserving measurement precision through the use of factory-calibrated disposable tips.

Inventive Principle:
Principle #21Skipping (Rushing through)

3Measurement precision

If needle probe tips are used for wafer testing, then measurement precision is improved, but object-generated harmful factors increase due to marking on test pads

Engineering Contradiction:
Improvetest measurement precisionVSAvoidprobe marking on pads
Core Design Contradiction:
Measurement precisionVSObject-generated harmful factors

Solution Approach 1:

The disposable probe tips are designed with a single-use lifecycle that eliminates the accumulation of marking issues. Each new tip starts fresh without previous contamination or wear, preventing the progressive marking problems that occur with reusable probes. The low cost of disposable tips makes this approach economically viable compared to maintaining reusable precision probes.

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

Solution Approach 2:

The patent extracts the harmful marking function from the measurement process by using probe tips that leave no permanent marks. The disposable nature of the tips ensures they are discarded before any significant marking can occur, effectively removing the harmful effect from the testing process while maintaining measurement precision through the tips' factory calibration.

Inventive Principle:
Principle #2Taking out (Extraction)

4Ease of manufacture

If flat probe tips are used for wafer testing, then ease of manufacture and cost are improved, but adaptability decreases because they can only contact soft materials

Engineering Contradiction:
Improveprobe card manufacturing easeVSAvoidmaterial compatibility
Core Design Contradiction:
Ease of manufactureVSAdaptability or versatility

Solution Approach 1:

The patent achieves universality by combining the simple flat tip geometry with a disposable design that allows different tip materials and configurations to be used interchangeably. This enables the same basic probe card structure to test both soft and hard materials by simply changing the disposable tip type, thereby achieving broad material compatibility without increasing manufacturing complexity of the underlying probe card system.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent changes the material parameters of the disposable probe tips to match the being tested. For hard materials, harder tip materials are used; for soft materials, softer tips are employed. This parameter adjustment at the tip level maintains the simple flat geometry for ease of manufacture while achieving versatility across different material types through material selection.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20240387297A1Semiconductor structure and test method thereof
Publication Date: 2024.11.21 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20240387297A1 patent drawing
  • US20240387297A1 patent drawing
  • US20240387297A1 patent drawing

AI summary

A semiconductor device includes a semiconductor die. The semiconductor die includes a device layer, an interconnect layer over the device layer, a conductive pad over the interconnect layer, a conductive seed layer directly on the conductive pad, and a passivation layer encapsulating the conductive pad and the conductive seed layer. The conductive pad is between the interconnect layer and the conductive seed layer.