Semiconductor Test Pad Circuit for Post-Packaging Memory Cell Verification
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Solution Overview
Problem
Existing semiconductor devices face challenges in testing memory cell defects after packaging, as it becomes difficult to apply test voltages to memory cells once they are packaged.
Innovation Solution
A semiconductor device design that includes an external test pad connected to an internal test pad, allowing a test voltage to be applied to word lines connected to memory cells, with a switch-like connection unit controlling the application of test or ground voltage based on mode signals, enabling effective testing of memory cells in a packaged state.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory cells are packaged, then device protection and commercial readiness are improved, but the ability to apply test voltages to memory cells deteriorates
Solution Approach 1:
The patent incorporates test pads and connection units into the packaged device structure in advance, enabling post-packaging testing capability. The internal test pads are pre-connected to word lines through connection units that can be activated during testing, allowing test voltages to be applied even after packaging without requiring device disassembly.
2Measurement precision
If test voltages are applied to word lines during testing, then memory cell defect detection is improved, but risk of device damage increases
Solution Approach 1:
The patent employs dynamic connection units (switches) that can be controlled to connect or disconnect test voltage paths based on testing requirements. The connection units allow flexible configuration of voltage application, enabling safe testing by controlling which word lines receive test voltages and isolating sensitive memory cells when not under test, thereby reducing damage risk while maintaining detection capability.
Data Source
AI summary
Provided is a semiconductor device capable of effectively testing whether memory cells and a memory cell array are defective. The semiconductor device may include a memory cell array having a plurality of memory cells and an external test pad connected to an internal test pad. A test voltage may be applied to the plurality of word lines connected to the plurality of memory cells via the external test pad and the internal test pad in a test mode, wherein the test voltage disables the plurality of word lines.