Semiconductor Test Structure for Isolated Substrate Pad Routing
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Solution Overview
Problem
In semiconductor testing structures, the limited space on a scrap line (SL) and the narrow width of the SL due to design rule constraints hinder the efficient placement of multiple devices with different dimensions and properties, leading to issues like current leakage and electrical drift during testing, as the well is directly connected to the substrate, causing unintended current paths when the wafer is placed on a measurement device chuck.
Innovation Solution
A semiconductor testing structure is formed by creating a first conductive wire at a preset distance from active areas on the substrate, with contact holes and a first metal layer connected to a common pad, allowing for efficient electrical connection and reducing current leakage by routing the substrate current through the conductive wire rather than the well, thus maintaining stable electrical performance during testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If multiple devices with different dimensions and properties are placed in a limited TEG space, then space utilization is improved, but current leakage and electrical drift occur during testing due to direct well-substrate connection
Solution Approach 1:
The substrate connection is segmented into two separate paths: one for current flow (through the well) and one for testing (through the conductive wire to common pad). This segmentation allows the well to remain directly connected to substrate for device operation while the testing path is isolated through the conductive wire structure, preventing current leakage during measurements.
Solution Approach 2:
The conductive wire acts as an intermediary element between the substrate and the measurement device chuck. By routing substrate current through this intermediate conductive wire to a common pad rather than direct substrate contact, the patent eliminates unintended current paths and prevents electrical drift during testing while maintaining full device functionality.
2Ease of manufacture
If the well is directly connected to the substrate, then device operation is simplified, but unintended current paths are created when the wafer is placed on a measurement device chuck
Solution Approach 1:
The conductive wire serves as an intermediary that redirects substrate current through a controlled path to the common pad, preventing direct contact between the substrate and measurement device chuck. This intermediary structure eliminates harmful current leakage while preserving the simplicity of device operation through the well-substrate connection.
Solution Approach 2:
The harmful direct substrate-chuck contact path is extracted and replaced with a controlled conductive wire path. By removing the direct electrical contact between substrate and measurement device, the patent eliminates current leakage while maintaining device operational simplicity through the well connection.
3Quantity of substance
If shared pads are used to connect sources, gates and substrates of multiple MOS transistors, then the quantity of used pads is reduced, but the complexity of electrical testing increases
Solution Approach 1:
The testing structure is segmented into device-specific contact holes and a shared common pad. Each MOS transistor connects to the common pad through its own contact hole and conductive wire path, allowing individual device testing while sharing the common pad infrastructure. This reduces pad quantity while maintaining testing simplicity through the standardized common pad interface.
Data Source
AI summary
A semiconductor testing structure forming method includes: a semiconductor substrate is provided, and the semiconductor substrate includes a plurality of active areas arranged separately; a first conductive wire is formed at a preset distance from the plurality of active areas in the semiconductor substrate, and the first conductive wire is connected with a substrate of a respective active device formed in each of the plurality of active areas; a plurality of first contact holes is formed on the first conductive wire; and a first metal layer is formed on top of each of the plurality of first contact holes to obtain the semiconductor testing structure, where the first metal layer is electrically connected with a first common pad and the first common pad is configured to perform an electric performance test on the semiconductor testing structure.