Semiconductor Test Pad Segmentation for Micro Bump Testing

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Solution Overview

Problem

The challenge lies in effectively testing semiconductor memory apparatuses with micro bumps, as the small size of these bumps makes direct testing difficult, and using larger test pads for testing is not feasible for high-density integration, necessitating a method to test these devices with a limited number of test pads.

Innovation Solution

A semiconductor integrated circuit system is developed with a test input/output port featuring multiple test pads, an internal input interface that generates internal signals and temporary storage data, and an error detection block to compare internal and temporary storage data, allowing for testing through a single test pad.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the size of test pads is increased to enable direct testing of micro bumps, then testing capability is improved, but the density of integrated circuits decreases

Engineering Contradiction:
Improvetesting capabilityVSAvoidpad area
Core Design Contradiction:
Measurement precisionVSArea of moving object

Solution Approach 1:

The test pad structure is segmented into multiple layers: an upper test pad layer with larger test pads for testing, and a lower signal pad layer with smaller signal pads for high-density integration. This segmentation allows each layer to serve its specific function optimally without compromising the other.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from a two-dimensional planar arrangement to a three-dimensional stacked structure by placing test pads and signal pads in different vertical layers. This dimensional change enables both large test pads and high-density signal pad integration to coexist in the same device footprint.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Quantity of substance

If the size of micro bumps is reduced for high-density integration, then integration density is improved, but direct testing with test equipment pins becomes difficult

Engineering Contradiction:
Improveintegration densityVSAvoidtesting difficulty
Core Design Contradiction:
Quantity of substanceVSDifficulty of detecting and measuring

Solution Approach 1:

The upper test pad acts as an intermediary structure between the micro bump and the test equipment pin. It transfers the testing function from the microscopic micro bump level to the macroscopic test pad level, enabling standard test equipment to test miniaturized micro bumps effectively.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The testing function is segmented and transferred to a separate structural element (the upper test pad) that is specifically designed for testing purposes, while the micro bump itself remains optimized for signal transmission and high-density integration.

Inventive Principle:
Principle #1Segmentation

3Quantity of substance

If a limited number of test pads are used to achieve high-density integration, then integration density is improved, but testing coverage and capability are reduced

Engineering Contradiction:
Improveintegration densityVSAvoidtesting coverage
Core Design Contradiction:
Quantity of substanceVSAdaptability or versatility

Solution Approach 1:

The upper test pad serves multiple functions: it acts as a test access point for testing micro bumps, provides a bonding pad for electrical connection, and maintains structural integrity. This multi-functionality allows comprehensive testing capability with minimal pad count.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The test pad structure is designed to serve itself by integrating the testing, bonding, and structural functions into a single element, eliminating the need for separate dedicated test pads and enabling high-density integration without sacrificing testing coverage.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS9279855B2Semiconductor integtrated circuit including test pads
Publication Date: 2016.03.08 SK HYNIX INC
  • US9279855B2 patent drawing
  • US9279855B2 patent drawing
  • US9279855B2 patent drawing

AI summary

A semiconductor integrated circuit includes a test input/output port including test pads; an internal input interface configured to generate an internal clock, an internal address, an internal command, internal data and temporary storage data in response to external signals through the test input/output port; and an error detection block configured to determine whether the internal data and the temporary storage data are the same, and output a result through one test pad of the port. The internal input interface includes a data input/output block which generates the internal data and the data input/output block includes a temporary storage part which stores the internal data as the temporary storage data, a data output part which receives the temporary storage data, and a data input part which receives an output of the data output part and outputs it as the internal data.