Semiconductor Package Test Pads Top Bottom Substrate
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Solution Overview
Problem
Conventional semiconductor packages face challenges in miniaturization due to the increasing need for test connections, as they typically provide test connections only on a single surface, which hinders the reduction of overall package size, especially in System in Package (SIP) and Package on Package (POP) devices.
Innovation Solution
The semiconductor package features test pads on both top and bottom surfaces of the substrate, with a first group having a smaller height and a second group with solder balls, allowing for dual test connections and reducing the substrate size by optimizing the layout and arrangement of test pads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If test connections are provided only on a single surface of the substrate, then the testing process is simple, but the substrate size increases to accommodate all necessary test connections
Solution Approach 1:
The patent transitions from providing all test connections on a single surface (2D arrangement) to distributing test connections across both top and bottom surfaces (3D spatial utilization). This dimensional expansion allows test pads to be arranged on multiple surfaces, effectively doubling the available test connection area without increasing the substrate footprint, thus resolving the contradiction between testing simplicity and substrate size.
2Adaptability or versatility
If the number of solder balls and connection pads is increased to meet connection needs, then the connectivity is improved, but the substrate area occupied increases
Solution Approach 1:
The patent utilizes both top and bottom surfaces of the substrate for mounting solder balls and connection pads, effectively distributing the connection elements across three-dimensional space. This approach allows a higher density of connection points without proportionally increasing the substrate area, as connections are arranged vertically and horizontally across multiple surfaces.
Solution Approach 2:
The patent divides the connection and testing functions into separate groups: user-defined connection pads and test-only pads. This segmentation allows optimization of each function's spatial arrangement, with test pads strategically placed on both surfaces to minimize area occupation while maintaining full testing capability.
3Area of stationary object
If the substrate size is reduced to meet miniaturization demands, then the product size decreases, but the space for test connections becomes insufficient
Solution Approach 1:
By utilizing both top and bottom surfaces of the substrate for test connections, the patent effectively doubles the available test connection area within the same substrate footprint. This dimensional approach allows miniaturization of the substrate while maintaining or even increasing the total test connection capacity, directly resolving the contradiction between substrate size reduction and test connection sufficiency.
Data Source
AI summary
A semiconductor package and testing method is disclosed. The package includes a substrate having top and bottom surfaces, a semiconductor chip mounted in a centrally located semiconductor chip mounting area of the substrate, and a plurality of test pads disposed on top and bottom surfaces of the substrate and comprising a first group of test pads configured on the top and bottom surfaces of the substrate and having a first height above the respective top and bottom surface of the substrate, and a second group of test pads disposed on the lower surface of the substrate and having a second height greater than the first, wherein each one of the second group of test pads includes a solder ball attached thereto.