Semiconductor Integrated Circuit Test Path Switching
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Solution Overview
Problem
The existing test methods for semiconductor integrated circuits, such as timing controllers, are inadequate due to the significant difference in transfer rates between the bus interface clock and the system clock, limiting the ability to efficiently test and control the data signal processor, especially with restricted test pattern lengths.
Innovation Solution
A semiconductor integrated circuit design that includes a data signal processor, a control bus portion with a slower operating clock, and a switching mechanism to selectively choose between a direct path for the control signal from outside and a path through the control bus, allowing for reliable testing and normal operation by bypassing the slower bus interface clock during testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If control signals are input through the control bus portion, then normal operation is maintained, but testing efficiency is reduced due to the slower bus clock rate
Solution Approach 1:
The patent divides the control signal input path into two separate paths: a first path through the control bus portion for normal operation, and a second direct path for testing. This segmentation allows each path to serve its specific function optimally without interfering with the other, resolving the contradiction between normal operation reliability and testing efficiency.
Solution Approach 2:
The patent introduces a switching portion that dynamically selects which path to use based on the operational mode (normal operation or testing). This dynamic switching capability allows the system to optimize performance for each mode, achieving both reliable normal operation and efficient testing by selecting the appropriate path at runtime.
2Speed
If test patterns are input at high speed, then testing speed is improved, but the control registers cannot be properly controlled due to the slower bus clock rate
Solution Approach 1:
The patent separates the control signal input path into a direct path for testing and a bus portion path for normal operation. During testing, the direct path allows high-speed test pattern input without being constrained by the slower bus clock rate, while the bus portion path maintains proper control register operation during normal use, thus resolving the contradiction between testing speed and control operation ease.
Solution Approach 2:
The switching portion acts as an intermediary that directs control signals to the appropriate path based on the operational mode. During testing, it routes signals through the direct path to enable high-speed input, while during normal operation, it routes signals through the bus portion to maintain proper control register operation, thereby mediating between the conflicting requirements of speed and ease of operation.
3Productivity
If the bus clock rate is increased to match the system clock rate, then testing efficiency is improved, but the control bus portion cannot properly control the data signal processor during normal operation
Solution Approach 1:
The patent divides the control signal transmission path into two separate paths with different clock rates: the direct path uses the system clock rate for high-speed testing, while the bus portion path uses the slower bus clock rate for reliable normal operation control. This segmentation allows each path to operate at its optimal clock rate without compromising the other, resolving the contradiction between testing efficiency and control reliability.
Solution Approach 2:
The switching portion dynamically selects which path to use based on the operational mode (testing or normal operation). During testing, it enables the direct path with system clock rate for high-speed operation, while during normal operation, it enables the bus portion path with its appropriate clock rate for reliable control, thus dynamically adapting to resolve the contradiction between productivity and reliability.
Data Source
AI summary
A first path for directly inputting a control signal from the outside to a data signal processor and a second path for inputting a control signal generated by a bus interface to the data signal processor can be selectively switched by a switching portion. At the test time of a timing controller, the first path is selected by the switching portion so that the control signal is directly input to the data signal processor without being passed through the bus interface having a slow operation clock, and thus the timing controller can be reliably tested. At the normal use time, the second path is selected by the switching portion, thereby the control signal is input via the bus interface to various kinds of processors such as the data signal processor, and thus the normal operation can be reliably treated.