Multi-Level Test Pattern for Semiconductor Interconnect Failure Detection
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Solution Overview
Problem
The semiconductor backend process faces challenges such as errors in design and processing during metal interconnect formation, leading to short-circuits or disconnections, which reduce manufacturing yield and increase costs, making it difficult to predict and prevent all potential failures in semiconductor device design.
Innovation Solution
A test pattern and method are developed that include variably positioned via patterns in metal interconnects, using an algorithm to detect open-circuit or short-circuit failures by forming specific line patterns and via structures on a substrate, allowing for accurate failure detection in a semiconductor device manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple via patterns are formed around intersection regions of metal interconnects, then reliability of connections is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The test pattern is divided into multiple levels (first level with first line patterns, second level with second line patterns, third level with via patterns). Each level serves a specific function in detecting different types of failures, allowing complex testing to be broken down into manageable segments that can be manufactured and analyzed separately.
Solution Approach 2:
The patent extends the test pattern into three dimensional levels with via patterns connecting different levels. This vertical dimension allows detection of through-via failures in addition to planar interconnect failures, comprehensively testing metal interconnect reliability without requiring excessive planar complexity.
2Measurement precision
If discontinuous regions are spaced apart by small first space, then detection precision of open-circuit failures is improved, but manufacturing precision requirements increase
Solution Approach 1:
The test pattern is designed with predetermined discontinuous regions at specific spacing before manufacturing. This preliminary design establishes known good patterns that should be continuous if manufacturing is successful, allowing detection of manufacturing defects without requiring ultra-precise spacing control during fabrication.
Solution Approach 2:
The via patterns formed around intersection regions serve as intermediaries that connect discontinuous regions across different metal layers. These via patterns provide a bridge that allows detection of open-circuit failures while compensating for manufacturing variations in the spacing between discontinuous regions.
3Reliability
If test pattern includes multiple levels with via patterns, then detection coverage of failure modes is improved, but productivity of manufacturing process decreases
Solution Approach 1:
The multi-level test pattern structure serves multiple functions simultaneously: it detects open-circuit failures in first and second metal interconnects, detects through-via failures, and detects short-circuit failures. This universal testing capability is achieved through a single integrated pattern design that can be manufactured in one process run, minimizing the impact on productivity.
4Reliability
If via patterns are formed around intersection regions, then reliability of via connections is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The via patterns are merged with the intersection regions of metal interconnects in the layout design. This combining of via placement with natural interconnect intersections allows the same manufacturing processes to create both functional interconnects and test vias simultaneously, reducing additional manufacturing steps and costs while improving via connection reliability through optimized positioning.
Data Source
AI summary
A test pattern includes first line patterns disposed at a first level, having discontinuous regions spaced apart by a first space, having a first width, and extending in a first direction. The test pattern includes a connection line pattern disposed at a second level and extending in the first direction, second line patterns disposed at the second level, branching from the connection line pattern, having a second width, and extending in a second direction perpendicular to the first direction. The test pattern includes via patterns disposed at a third level, having a third width, and formed around an intersection region having the first width of the first line pattern and the second width of the second line pattern. First pads are connected with the first line patterns. A second pad is connected with the connection line pattern.