Semiconductor Test Pattern Layout for Precise Overlay Measurement
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Solution Overview
Problem
As semiconductor pattern sizes decrease, overlay consistency between layers deteriorates, necessitating improved methods for aligning and measuring overlay patterns in semiconductor devices to maintain accuracy and efficiency.
Innovation Solution
A semiconductor device design featuring adjacent first and second test patterns with overlapping marks at different vertical levels and varying pitches, allowing for improved overlay measurement without occupying large substrate space, utilizing both optical and scanning electron microscope methods for precise alignment and inspection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If separate overlay patterns are arranged on the substrate for overlay measurement, then overlay consistency can be measured, but the substrate space required increases
Solution Approach 1:
The patent combines the overlay pattern and test element group into a single integrated test structure. The overlay pattern includes both overlay marks and test element marks arranged in an interlaced manner, allowing simultaneous measurement of overlay consistency and test element performance without requiring separate substrate areas for each function.
Solution Approach 2:
The integrated test structure serves multiple functions: it performs overlay measurement between different vertical levels, provides test element evaluation, and enables space-efficient substrate utilization. The same physical structure accomplishes what previously required separate dedicated overlay patterns and test element groups.
2Productivity
If pattern sizes are reduced to increase device density, then more devices fit on substrate, but overlay consistency deteriorates
Solution Approach 1:
The overlay pattern utilizes multiple vertical levels with marks positioned at different heights. This three-dimensional arrangement allows overlay measurement across vertical layers while maintaining small horizontal footprint, enabling high device density without sacrificing overlay measurement capability.
Solution Approach 2:
The overlay pattern is segmented into multiple lower marks and upper marks at different vertical levels. This segmentation allows independent positioning and measurement of each layer's overlay accuracy, enabling precise overlay control even as overall pattern dimensions are reduced for higher device density.
Data Source
AI summary
A semiconductor device includes a semiconductor substrate, a first test pattern disposed on the semiconductor substrate, and a second test pattern located adjacent to the first test pattern. The first test pattern includes an overlay pattern, and the second test pattern includes a test element group.