Semiconductor Test Probe Alignment via Auxiliary Signal Detection

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Manual verification of alignment between test probes and test keys in semiconductor device testing is inefficient and inaccurate, potentially damaging the semiconductor device due to misalignment.

Innovation Solution

A method and apparatus that utilize auxiliary pins and pads to obtain an alignment signal through vertical alignment and gradual contact, ensuring accurate alignment before performing a probing test, using a controller and driving mechanism to verify the alignment signal meets a condition before electrical contact.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If manual verification of alignment between test probes and test keys is performed, then alignment can be checked, but the process is inefficient and inaccurate, potentially damaging the semiconductor device

Engineering Contradiction:
Improvealignment accuracyVSAvoidtesting efficiency
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The patent replaces manual mechanical alignment verification with an automated optical measurement system. The alignment signal detection mechanism uses optical or electrical fields to automatically detect and verify the alignment between test pins and test pads, eliminating manual intervention while achieving high precision and efficiency simultaneously.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent introduces an alignment signal as an intermediary element between the test probe and semiconductor device. This alignment signal serves as a mediator that provides objective feedback on alignment status, enabling automated verification without manual inspection while preventing damage through early detection of misalignment conditions.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If test probe is moved to contact with test key, then electrical connection can be established, but misalignment may cause damage to the semiconductor device

Engineering Contradiction:
Improveelectrical connection reliabilityVSAvoiddamage risk to semiconductor device
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent performs preliminary alignment verification using alignment signals before the test probe makes full electrical contact with the test key. This preliminary action detects potential misalignment issues in advance, allowing the system to prevent damaging contact while ensuring reliable electrical connections when alignment is correct.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements a feedback mechanism where alignment signals provide real-time information about the alignment status between test pins and test pads. This feedback loop enables the system to adjust the test probe position or halt the approach movement when misalignment is detected, preventing damage while ensuring reliable electrical connection establishment.

Inventive Principle:
Principle #23Feedback

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Prevents damage to semiconductor devices by ensuring precise alignment between test probes and test keys, improving the accuracy and efficiency of semiconductor device testing.

Implementation Method 1

gradually reducing a vertical distance between the one or more auxiliary pins of the test probe and the one or more auxiliary pads of the test key for bringing into an electrical contact until the alignment signal there-between satisfies an alignment condition

Methodology Applied
Scientific EffectElectrical contact: Conduction (electrical)

Data Source

PatentUS12066460B2Method and apparatus for testing semiconductor device
Publication Date: 2024.08.20 YANGTZE MEMORY TECH CO LTD
  • US12066460B2 patent drawing
  • US12066460B2 patent drawing
  • US12066460B2 patent drawing

AI summary

A method for testing a semiconductor device comprises obtaining an alignment signal between one or more auxiliary pins of a test probe and one or more auxiliary pads of a test key of the semiconductor device before a probing test of the semiconductor device. The obtaining of the alignment signal comprises: performing a vertical alignment between the one or more auxiliary pins of the test probe and the one or more auxiliary pads of the test key; and gradually reducing a vertical distance between the one or more auxiliary pins of the test probe and the one or more auxiliary pads of the test key for bringing into an electrical contact until the alignment signal there-between satisfies an alignment condition.