Semiconductor Test Quality Evaluation Using Weighted Fault Dictionary
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Solution Overview
Problem
Current test quality evaluation methods for semiconductor integrated circuits are inadequate in accurately estimating failure remaining rates due to insufficient correlation between fault coverage and failure occurrence rates, especially with the introduction of new fault models, leading to increased test costs and resource requirements.
Innovation Solution
A test quality evaluating and improving system that creates a weighted fault dictionary by correlating layout elements with undetected faults, using a failure mode-fault model correlation factor and failure occurrence rates to calculate a failure remaining rate, and inserts test points to preferentially detect high-weight undetected faults, thereby improving test quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all fault models are considered and test patterns corresponding to the respective models are generated, then test quality is improved, but resources and patterns are considerably increased (test cost is also increased)
Solution Approach 1:
The patent changes the parameter of fault model consideration from comprehensive (all models) to selective (significant models only). It introduces a mechanism to identify and prioritize fault models based on their significance to the specific circuit design, thereby reducing the number of test patterns needed while maintaining adequate test quality coverage for critical failure modes
Solution Approach 2:
The patent applies local quality by tailoring the fault model selection to the specific characteristics of each circuit design. Instead of uniformly applying all fault models to all circuits, it identifies which fault models are most relevant to particular circuit structures, wiring patterns, and design features, thereby optimizing test resources for each specific case
2Reliability
If all fault models are considered and test patterns corresponding to the respective models are generated, then test quality is improved, but test cost is increased
Solution Approach 1:
The patent modifies the parameter of fault model comprehensiveness to balance test quality with cost. It introduces a significance assessment mechanism that determines which fault models warrant the investment in generating corresponding test patterns, thereby reducing unnecessary test costs while maintaining coverage of critical failure modes
Solution Approach 2:
The patent applies partial action by generating test patterns for only the most significant fault models rather than all possible fault models. This selective approach provides sufficient test quality for critical failures while avoiding the excessive cost of comprehensive testing for all potential failure modes
3Ease of operation
If traditional fault coverage formulas are used, then calculation is simple, but accuracy in estimating failure remaining rate is insufficient
Solution Approach 1:
The patent enhances the traditional fault coverage formula by introducing additional parameters: fault model significance weights and failure occurrence rates. These parameters transform the simple binary coverage calculation into a weighted summation that reflects both the importance of different fault models and their actual occurrence probabilities in the specific circuit context
Solution Approach 2:
The patent introduces an intermediary calculation layer between simple fault coverage and actual failure remaining rate. The new formula acts as a mediator that incorporates fault model significance and failure occurrence rate as intermediate factors, providing a more accurate estimation without requiring complete fault simulation for all models
Data Source
AI summary
A test quality evaluating and improving system has a fault-layout information link section which creates a weighted fault dictionary by correlating a layout element related to an undetected fault, out of faults corresponding to a specified fault model and occurring in a circuit to be tested, with the undetected fault as a weight of the undetected fault which cannot be detected by a test pattern for testing the faults; a test quality measure calculating section which multiplies the weight of the undetected fault, the failure mode-fault model correlation factor for correlating the failure mode of the layout element and the fault model, and the failure occurrence rate of each layout element, and outputs an obtained product as a failure remaining rate of the test pattern; a determining section; and a test point inserting section.