Semiconductor Test Structure with Rounded Active Regions

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Solution Overview

Problem

Current semiconductor device test structures fail to effectively evaluate electrical characteristics due to variations in active region shapes and corner rounding effects, which affect the performance of fin field effect transistors.

Innovation Solution

The semiconductor device incorporates test structures with active regions having rounded corner portions, where gate electrodes and electrode patterns are positioned to evaluate electrical shorts and variability, allowing for the measurement of current flow and electrical characteristics across different overlapping areas.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If test structures use standard active regions with sharp corners, then manufacturing is simpler, but measurement precision of electrical characteristics deteriorates due to corner rounding effects

Engineering Contradiction:
Improveelectrical characteristic measurement precisionVSAvoidactive region shape control
Core Design Contradiction:
Measurement precisionVSManufacturing precision

Solution Approach 1:

The patent changes the geometric parameter of the active region from sharp corners to rounded corners with controlled radius. This parameter change allows the test structure to account for corner rounding effects that occur during manufacturing, thereby improving the precision of electrical characteristic measurements while the rounding radius is controlled to maintain manufacturing feasibility

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent creates test structures that copy the rounded corner geometry found in actual device fabrication. By replicating the rounded corner shape in the test structure, measurements taken from these structures accurately reflect the electrical characteristics of manufactured devices, improving measurement precision without requiring separate validation processes

Inventive Principle:
Principle #26Copying

2Productivity

If test structures evaluate multiple electrical characteristics simultaneously, then productivity increases, but device complexity increases

Engineering Contradiction:
Improvetest evaluation efficiencyVSAvoidtest structure complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent designs test structures with active regions, gate electrodes, and electrode patterns that can simultaneously evaluate multiple electrical characteristics including current flow, electrical shorts, and corner rounding effects. This multi-functional design allows a single test structure to perform several evaluation functions, improving productivity while the modular configuration helps manage complexity

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Measurement precision

If electrode patterns overlap more with active patterns, then electrical characteristic measurement improves, but manufacturing precision requirements increase

Engineering Contradiction:
Improveelectrical short detection precisionVSAvoidelectrode pattern positioning
Core Design Contradiction:
Measurement precisionVSManufacturing precision

Solution Approach 1:

The patent optimizes the overlap parameter between electrode patterns and active patterns to achieve an optimal balance. By carefully controlling the degree and position of overlap, the test structure achieves high precision in detecting electrical shorts and other electrical characteristics while keeping the positioning requirements within manufacturing capabilities

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS9337112B2Semiconductor device having test structure
Publication Date: 2016.05.10 SAMSUNG ELECTRONICS CO LTD
  • US9337112B2 patent drawing
  • US9337112B2 patent drawing
  • US9337112B2 patent drawing

AI summary

A semiconductor device is provided. First and second pads are electrically connected to a plurality of test structures. Each test structure includes an active region, active patterns, gate electrodes and an electrode pattern. The active region includes a rounded corner portion. The active patterns protrudes from the semiconductor substrate and extends in parallel in a first direction. The gate electrodes crosses over the active patterns in a second direction. One gate electrode is electrically connected to the first pad. The electrode pattern is disposed at a side of the gate electrode electrically connected to the first pad. The electrode pattern is electrically connected to the second pad. The electrode pattern crosses over the active patterns. An overlapping area of the electrode pattern and the active patterns in each test structure is different from an overlapping area of the electrode pattern and the active patterns in other test structures.