Semiconductor Chip Test Scan Chain for Micro Bump Connectivity

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Solution Overview

Problem

In stack memory devices using micro bumps for electrical coupling, direct probing tests are impractical, leading to contamination and increased risks of open or short circuits, making it difficult to detect leakage currents in input/output buffers.

Innovation Solution

A test scan chain is implemented on semiconductor chips to output data to nodes electrically coupled with micro bumps, store data corresponding to capacitance, and output it back, allowing for the detection of connectivity failures without direct probing, using a boundary scan test method.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If direct probing is performed on micro bumps for testing, then test accessibility is improved, but bump contamination and shape deformation occur leading to poor electrical coupling

Engineering Contradiction:
Improvetest accessibilityVSAvoidelectrical coupling quality
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The patent introduces an intermediary testing mechanism that does not require direct contact with the micro bumps. Instead of probing the bumps directly, the testing method uses electrical signals transmitted through the bumps to detect connectivity and leakage current. This intermediary approach allows testing while preserving the integrity of the bumps and ensuring reliable electrical coupling.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent replaces the mechanical probing system with an electrical testing system. Rather than using physical probe pins to contact and test the micro bumps, the invention uses electrical signals transmitted through the bumps to detect connectivity and leakage current. This substitution eliminates mechanical contact that causes contamination and deformation, while still achieving comprehensive testing.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Productivity

If micro bumps are contaminated after testing, then testing can be performed, but open circuit or short circuit failures are likely to occur

Engineering Contradiction:
Improvetesting capabilityVSAvoidcircuit integrity
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent uses an intermediary testing approach that transmits electrical signals through the micro bumps without direct physical contact. This allows testing capability to be maintained while preventing contamination that would lead to open or short circuit failures. The intermediary electrical signal method preserves circuit integrity throughout the testing process.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If leakage current occurs in bumped electric coupling, then electrical coupling is established, but detecting the leakage current becomes difficult

Engineering Contradiction:
Improveelectrical couplingVSAvoidleakage current detection
Core Design Contradiction:
ReliabilityVSDifficulty of detecting and measuring

Solution Approach 1:

The patent implements a feedback mechanism where electrical signals are transmitted through the micro bumps and the responses are analyzed to detect leakage current. By monitoring the electrical characteristics of the bumps during signal transmission, the system can identify abnormal current leakage while maintaining functional electrical coupling. The feedback loop enables continuous monitoring and detection of leakage current without compromising coupling reliability.

Inventive Principle:
Principle #23Feedback

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enables effective testing of micro bump connectivity and leakage current detection in stack chips without physical contact, reducing the risk of contamination and improving the reliability of chip stacking by identifying potential failures such as open or short circuits.

Implementation Method 1

store data corresponding to capacitance of the node by floating the node for a predetermined time, and output data corresponding to the stored capacitance

Methodology Applied
Scientific EffectCapacitance: Capacitance

Data Source

PatentUS9459318B2Semiconductor chip, stack chip including the same, and testing method thereof
Publication Date: 2016.10.04 SK HYNIX INC
  • US9459318B2 patent drawing
  • US9459318B2 patent drawing
  • US9459318B2 patent drawing

AI summary

A semiconductor chip includes an input pad and an output pad formed on the semiconductor chip; at least one bump formed on the semiconductor chip; and a test scan chain configured to output data applied from the input pad, to a node which is electrically coupled with the bump, store data corresponding to capacitance of the node by floating the node for a predetermined time, and output data corresponding to the stored capacitance, to the output pad.