Semiconductor Test Device Segmentation Reduces I/O Burst Length
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Solution Overview
Problem
The existing automatic test equipment (ATE) for semiconductor devices faces challenges in reducing test time due to physically restricted input/output resources, leading to increased burst lengths of test signals and consequently higher manufacturing costs.
Innovation Solution
A test device with an integer number of input and output resources is designed to receive an integer number of test signals from devices under test on a wafer, incorporating a comparative circuit to generate test result signals and a memory to store bad cell and repair information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of input/output resources of ATE is physically restricted, then the burst length of test signals must be increased, but this increases the test time required to test semiconductor devices
Solution Approach 1:
The patent segments the test process by dividing the wafer into multiple regions and using multiple probe groups, where each probe group can independently test different regions simultaneously. This segmentation allows parallel testing, effectively reducing test time despite limited input/output resources.
Solution Approach 2:
The patent transitions from sequential testing along a single dimension to two-dimensional parallel testing by arranging multiple probe groups in different spatial locations on the wafer. This dimensional approach enables simultaneous testing of multiple devices, overcoming the bottleneck of limited I/O resources.
2Quantity of substance
If the burst length of test signals is increased due to restricted input/output resources, then fewer input/output terminals are needed, but manufacturing costs increase
Solution Approach 1:
By segmenting the testing into multiple parallel probe groups, the patent reduces the burst length required for each group while maintaining overall testing efficiency. This allows the use of fewer I/O terminals per probe group, reducing manufacturing costs without sacrificing test coverage.
Solution Approach 2:
The patent changes the parameter of burst length from a long sequential transmission to shorter parallel transmissions across multiple probe groups. This parameter optimization reduces the complexity and cost of I/O terminal requirements while maintaining test effectiveness.
Data Source
AI summary
A test device includes a plurality of input/output terminals configured to be electrically connected to the devices formed on the wafer, a comparative circuit configured to receive a plurality of test signals from a device under test formed on the wafer, and generate a plurality of test result signals, based on the plurality of test signals, and a memory configured to receive the plurality of test result signals and store bad cell information and repair information related to the device under test, which are indicated by the plurality of test result signals, wherein the total number of the plurality of test signals received from the device under test at one time is an integer.