Semiconductor Test Circuit Using Shift Register for Signal Selection
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Solution Overview
Problem
The increasing number of test signals in semiconductor devices leads to a significant increase in the surface area of the interconnect region, hindering the reduction of chip size and making it difficult to detect proper signal transfer due to poor monitorability of test signals.
Innovation Solution
A semiconductor device with a test circuit that includes a decoder, a selector, and a plurality of registers, where the selector sequentially selects and outputs test signals, and a shift clock generating circuit generates shift clocks corresponding to the number of control circuits, allowing for reduced interconnects and improved monitorability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of test signals is increased to perform comprehensive operational testing, then the testing capability is improved, but the surface area of the interconnect region increases significantly
Solution Approach 1:
The test signals are segmented and stored in a shift register composed of multiple flip-flops rather than being transmitted simultaneously through multiple interconnect lines. The selector sequentially selects and transmits individual test signals, dividing the parallel transmission into sequential serial transmission, thus reducing interconnect requirements.
Solution Approach 2:
The patent transitions from parallel transmission in the spatial domain (multiple simultaneous signal lines) to sequential transmission in the time domain (one signal line used at different time intervals). The shift register stores test signals across multiple time cycles, allowing comprehensive testing using a single interconnect path.
2Adaptability or versatility
If more test signals are added to cover more internal circuitry, then the operational test coverage is improved, but the chip size increases
Solution Approach 1:
The shift register and selector mechanism serves multiple functions: it stores multiple test signals, sequentially selects them, and transmits them through a single interconnect path. This multi-functional design eliminates the need for separate dedicated interconnect lines for each test signal, reducing overall chip area while maintaining comprehensive test coverage.
Solution Approach 2:
The shift register acts as an intermediary storage element between the test signal source and the internal circuitry under test. It buffers and manages multiple test signals, allowing them to be transmitted sequentially through a single interconnect path rather than requiring direct simultaneous connections to all target circuits.
3Speed
If multiple test signals are transmitted simultaneously through separate interconnects, then the signal transfer speed is improved, but the monitorability of test signals deteriorates
Solution Approach 1:
The patent extracts the monitoring function from the complex parallel signal environment and applies it to the simplified sequential single-line transmission. By transmitting one test signal at a time through a dedicated selector output, the monitoring point can clearly observe each signal's transfer status without the interference and complexity of multiple simultaneous signals.
Data Source
AI summary
A device includes a decoder, a selector, and a plurality of registers. The decoder is configured to generate a plurality of test signals. The selector is coupled to the decoder. The selector is configured to sequentially select a test signal from the plurality of test signals and to sequentially output the test signal selected. The plurality of registers is coupled in series to each other. The plurality of registers includes a first stage register. The first stage register is coupled to the selector to sequentially receive the test signal from the selector.