Semiconductor Test Signal Generation Logic
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Solution Overview
Problem
Semiconductor devices lack an efficient mechanism for generating and decoding test signals to effectively evaluate normal and fuse test circuits, leading to incomplete testing and potential chip failure sorting errors.
Innovation Solution
Incorporating a normal test signal generator and a termination signal generator that respond to specific logic combinations of code signals to produce enablement and pulse signals, enabling the decoding of test address signals into respective test signals, and generating termination signals based on predetermined normal and fuse test signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a normal test signal generator and termination signal generator are implemented with specific logic combination responses, then test signal generation accuracy is improved, but device complexity increases
Solution Approach 1:
The test signal generator is divided into multiple independent components: a normal test signal generator for standard testing and a termination signal generator for specific termination conditions. Each generator processes different logic combinations independently, allowing precise test signal generation without requiring a completely complex redesign of the entire system.
Solution Approach 2:
The termination signal generator is configured to respond to specific logic combinations in advance, preparing termination signals before they are needed. This preliminary configuration allows the system to quickly switch between normal testing and termination modes without adding significant operational complexity during actual testing.
2Adaptability or versatility
If decoding of test address signals is implemented to generate multiple normal test signals, then test circuit evaluation capability is improved, but device complexity increases
Solution Approach 1:
The normal test signal generator is designed with a decoder that can process test address signals and generate multiple different normal test signals based on the decoded information. This multi-functional capability allows a single generator to handle various test circuits and configurations, improving evaluation capability without requiring separate generators for each test type.
3Reliability
If termination signals are generated based on predetermined normal and fuse test signals, then chip sorting accuracy is improved, but measurement precision requirements increase
Solution Approach 1:
The termination signal generator acts as an intermediary component that receives both normal test signals and fuse test signals as inputs, processes them according to predetermined logic combinations, and generates termination signals based on the combined information. This intermediary function allows the system to achieve high chip sorting accuracy by综合考虑 multiple test results without requiring any single signal detection to be perfectly precise.
Data Source
AI summary
A semiconductor device includes a normal test signal generator and a termination signal generator. The normal test signal generator is suitable for generating a first enablement signal and a first pulse signal in response to an external command signal when a first code signal and a second code signal have a predetermined logic combination. Further, the normal test signal generator is suitable for decoding a first test address signal and a second test address signal to generate first to fourth normal test signals. The termination signal generator is suitable for receiving the first pulse signal during an enablement period of the first enablement signal to generate a first termination signal which is enabled when a predetermined signal among the first to fourth normal test signals is generated.