Semiconductor Test Apparatus Signal Multiplexing for Area Efficiency

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Solution Overview

Problem

Conventional semiconductor integrated circuits require a large number of test signals to perform multiple test modes, leading to inefficient use of signal lines and reduced area efficiency.

Innovation Solution

A test apparatus for semiconductor integrated circuits that generates a test fuse signal in response to a test mode signal during testing and based on fuse status after testing, using a combination signal generating unit to store and output test signals, and a code signal generating unit to activate test code signals, allowing for multiple test modes with a fixed number of test signals.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple test apparatuses are provided to execute multiple test modes, then test capability is improved, but the number of test signals increases leading to reduced area efficiency

Engineering Contradiction:

Improvetest capabilityVSAvoidarea efficiency

Core Design Contradiction:

Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The test apparatus is designed to perform multiple test modes using a fixed number of test signals. The combination signal generating unit and code signal generating unit enable the same hardware to execute different test modes (first test mode and second test mode) by generating different test code signals, thus achieving multi-functionality without increasing the number of physical test signals or expanding the chip area.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If the number of test signals is increased to support multiple test modes, then test versatility is improved, but signal line area increases reducing area efficiency

Engineering Contradiction:

Improvetest mode varietyVSAvoidnumber of test signals

Core Design Contradiction:

Adaptability or versatilityVSQuantity of substance

Solution Approach 1:

A fixed number of test signals are made versatile through the combination signal generating unit and code signal generating unit. These units generate different test code signals from the same input test signals depending on the test mode, allowing one set of physical signal lines to support multiple test modes without increasing the quantity of test signals.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The test apparatus dynamically generates different test code signals based on the activated test mode. When a test mode signal is activated, the combination signal generating unit and code signal generating unit dynamically produce the appropriate test code signals for that mode, enabling the system to adapt its signal generation to different test requirements without adding permanent hardware for each mode.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS8149639B2Test apparatus of semiconductor integrated circuit and method using the same

Publication Date: 2012.04.03 SK HYNIX INC

AI summary

A test apparatus includes a test fuse unit for generating a test fuse signal in response to a test mode signal during a test time and generating a test fuse signals according to a fuse cutting after a termination of the test time, a combination signal generating unit for storing a test signal and inactivating a combination signal when the test mode signal is inactivate and for outputting the stored test signal as the combination signal when the test mode signal is activate, and a code signal generating unit for activating a test code signal when one of the test fuse signal and the combination signal is activated.